LTC2315-12 Datasheet, PDF (5/20 Pages) Linear Technology – 12-Bit, 5Msps Serial Sampling ADC in TSOT

LTC2315-12
adc timing characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
f_SAMPLE(MAX)
f_SCK
t_SCK
t_THROUGHPUT
t_CONV
t_ACQ
t₁
t₂
t₃
t₄
t₅
t₆
t₇
t₈
t₉
t₁₀
Maximum Sampling Frequency
Shift Clock Frequency
Shift Clock Period
Minimum Throughput Time, t_ACQ + t_CONV
Conversion Time
Acquisition Time
Minimum CS Pulse Width
SCK Setup Time After CS↓
SDO Enable Time After CS↓
SDO Data Valid Access Time after SCK↓
SCLK Low Time
SCLK High Time
SDO Data Valid Hold Time After SCK↓
SDO into Hi-Z State Time After 16th SCK↓
SDO into Hi-Z State Time After CS↑
CS↑ Setup Time After 14th SCK↓
Latency
(Notes 8, 9)
(Notes 8, 9)
(Note 8)
(Note 8)
(Notes 8, 9)
(Notes 8, 9, 10)
(Notes 8, 9, 10)
(Notes 8, 9)
(Notes 8, 9)
(Note 8)
l
5
MHz
l
87.5
MHz
l 11.4
ns
l
200
ns
l 160
ns
l 40
ns
l
5
ns
l
5
ns
l
6
ns
l
9.1
ns
l 4.5
ns
l 4.5
ns
l
1
ns
l
3
6
ns
l
3
6
ns
l
5
ns
l
1 Cycle Latency
t_WAKE__NAP Power-up Time from Nap Mode
t_WAKE__SLEEP Power-up Time from Sleep Mode
See Nap Mode section
See Sleep Mode section
50
ns
1.1
ms
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltage values are with respect to ground.
Note 3. When these pin voltages are taken below ground or above V_DD
(A_IN, REF) or OV_DD (SCK, CS, SDO) they will be clamped by internal
diodes. This product can handle input currents up to 100mA below ground
or above V_DD or OV_DD without latch-up.
Note 4. V_DD = 5V, OV_DD = 2.5V, f_SMPL = 5MHz, f_SCK = 87.5MHz, A_IN =
–1dBFS and internal reference unless otherwise noted.
Note 5. Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6. Linearity, offset and gain specifications apply for a single-ended
A_IN input with respect to ground.
Note 7. Typical RMS noise at code transitions.
Note 8. Parameter tested and guaranteed at OV_DD = 2.5V. All input signals
are specified with t_r = t_f = 1nS (10% to 90% of OV_DD) and timed from a
voltage level of OV_DD/2.
Note 9. All timing specifications given are with a 10pF capacitance load.
Load capacitances greater than this will require a digital buffer.
Note 10. The time required for the output to cross the V_IH or V_IL voltage.
Note 11. Guaranteed by design, not subject to test.
Note 12. Recommended operating conditions.
For more information www.linear.com/2315-12
231512f
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