LTC1043_15 Datasheet, PDF (5/16 Pages) Linear Technology – Dual Precision Instrumentation Switched Capacitor Building Block

TEST CIRCUITS
Test Circuit 1. Leakage Current Test
(7, 13, 6, 18)
A
+
0V TO 10V
(8, 14, 5, 15)
(11, 12, 2, 3)
NOTE: TO OPEN SWITCHES,
S1 AND S3
SHOULD BE CONNECTED
TO V–. TO OPEN S2, S4,
C_OSC PIN SHOULD BE
TO V+ C_OSC
LTC1043 • TC01
Test Circuit 3. Oscillator Frequency, f_OSC
(TEST PIN) 2
V+
+
4
5
+
6
IV
LTC1043
V– ₁₇
16
C_OSC
LTC1043 • TC03
APPLICATIO S I FOR ATIO
Common Mode Rejection Ratio (CMRR)
The LTC1043, when used as a differential to single-ended
converter rejects common mode signals and preserves
differential voltages (Figure 1). Unlike other techniques,
the LTC1043’s CMRR does not degrade with increasing
common mode voltage frequency. During the sampling
mode, the impedance of Pins 2, 3 (and 11, 12) should be
reasonably balanced, otherwise, common mode signals
will appear differentially. The value of the CMRR depends
on the value of the sampling and holding capacitors
(C_S, C_H) and on the sampling frequency. Since the
common mode voltages are not sampled, the
common mode signal frequency can well exceed the
sampling frequency without experiencing aliasing
phenomena. The CMRR of Figure 1 is measured by
LTC1043
Test Circuit 2. R_ON Test
(7, 13, 6, 18)
(8, 14, 5, 15)
+
VIN
100µA to 1mA
CURRENT SOURCE
(11, 12, 2, 3)
A
LTC1043 • TC02
Test Circuit 4. CMRR Test
7
8
V_OUT
10
11
1µF
12
+
CAPACITORS ARE
1µF _{NOT ELECTROLYTIC}
13
14
+ _{V– ≤ VCM ≤ V+}
( ) ^{CMRR = 20 LOG}
V_CM
V_OUT
NOTE: FOR OPTIMUM CMRR, THE C_OSC SHOULD
BE LARGER THAN 0.0047µF, AND
THE SAMPLING CAPACITOR ACROSS
PINS 11 AND 12 SHOULD BE PLACED
OVER A SHIELD TIED TO PIN 10
LTC1043 • TC04
1/2 LTC1043
7
8
+
V_D
C⁺ 11
C_S
C^– 12
+
V_D
C_H
13
14
+
V_CM
C_S, C_H ARE MYLAR OR POLYSTRENE
LTC1043 • AI01
Figure 1. Differential to Single-Ended Converter
1043fa
5