LTC5100 Datasheet, PDF (46/52 Pages) Linear Technology – 3.3V, 3.2Gbps VCSEL Driver

LTC5100
REGISTER DEFI ITIO S
Table 29. Register: IM_DAC—Modulation Current DAC (I²C Command Code 0x02)
REGISTER
.BITFIELD
RESET VALUE
BIT
(BIN)
FUNCTION AND VALUES
.Reserved
15:10
.Im_dac
9
0
DAC Setting for the Peak-to-Peak Modulation Current (the Combined MODA and MODB Pin Currents)
8
0
Read Access to This DAC is Always Available. Write Access is Only Valid if LPC_en = 0.
7
6
0
0
I_M
=
Im_dac
1024
• (Im_ rng
+
1) • 9mA
(typical)
5
0
4
0
3
0
2
0
1
0
0
0
Table 30. Register: PWR_LIMIT_DAC—Optical Power Limit DAC—Read Only (I²C Command Code 0x03)
REGISTER
.BITFIELD
RESET VALUE
BIT
(BIN)
FUNCTION AND VALUES
.Reserved
15:7
.pwr_limit_dac
6
Read Only
5
0
DAC Setting for the Over and Underpower Fault Detection Comparator (Read Only)
0
This Bit Field Has Different Functions Depending on Apc_en.
4
0
Constant Current Control (CCC) Mode (Apc_en = 0): Pwr_limit_dac Has No Function in This Mode.
3
0
Its Contents are Undefined.
2
0
Automatic Power Control (APC) Mode (Apc_en = 1): Pwr_limit_dac Tracks the Value of the Monitor
1
0
Diode Current. The Laser Power Controller Continuously Updates the PWR_LIMIT_DAC with the
0
0
Most Recent ADC Reading of Imd. Reading the DAC Will Return the Value of Imd_adc Shifted Right
by Three Bits.
46
sn5100 5100fs