LTC1760_11 Datasheet, PDF (40/48 Pages) Linear Technology – Dual Smart Battery System Manager Available in 48-Lead TSSOP Package

LTC1760
APPLICATIONS INFORMATION
Calculating IC Power Dissipation
The power dissipation of the LTC1760 is dependent
upon the gate charge of Q_TG and Q_BG.(Refer to Typical
Application). The gate charge is determined from the
manufacturer’s data sheet and is dependent upon both the
gate voltage swing and the drain voltage swing of the FET.
P_D = (V_DCIN – V_VCC) • f_OSC • (Q_TG + Q_BG) + V_DCIN •
I_{DCIN_CHG} – V_VCC • (I_SAFETY1 + I_SAFETY2)
where:
I_{DCIN_CHG}, I_SAFETY1, I_SAFETY2 are defined in the
previous section.
Example:
V_VCC = 5.2V, V_DCIN = 19V, f_OSC = 345kHz, Q_TG =
Q_BG = 15nC, I_{DCIN_CHG} = 2.62mA, I_SAFETY1 =
I_SAFETY2 = 218μA.
P_D = 190mW
V_SET/I_SET Capacitors
Capacitor C7 is used to filter the delta-sigma modulation
frequency components to a level which is essentially DC.
Acceptable voltage ripple at I_SET is about 10mV_P-P. Since
the period of the delta-sigma switch closure, T_ΔΣ, is about
10μs and the internal I_DAC resistor, R_SET, is 18.77k, the
ripple voltage can be approximated by:
ΔV_ISET
=
V_REF • T_{Δ ∑}
R_SET • C7
Then the equation to extract C7 is:
C7 = ^{VREF • TΔ ∑}
ΔV_ISET • R_SET
= 0.8/0.01/18.77k(10μs) ≅ 0.043μF
In order to prevent overshoot during start-up transients
the time constant associated with C7 must be shorter than
the time constant of C5 at the I_TH pin. If C7 is increased
to improve ripple rejection, then C5 should be increased
proportionally and charger response time to average cur-
rent variation will degrade.
Capacitors C_B1 and C_B2 are used to filter the V_DAC delta-
sigma modulation frequency components to a level which
is essentially DC. C_B2 is the primary filter capacitor and
CB1 is used to provide a zero in the response to cancel
the pole associated with C_B2. Acceptable voltage ripple
at V_SET is about 10mV_P-P. Since the period of the delta-
sigma switch closure, T_ΔΣ, is about 11μs and the internal
V_DAC resistor, R_VSET, is 7.2kΩ, the ripple voltage can be
approximated by:
( ) ^ΔVVSET
=
V_REF • T_{Δ ∑}
R_VSET C_B1||C_B2
Then the equation to extract C_B1 || C_B2 is:
C_B1 || C_B2
=
V_REF
R_VSET
• T_{Δ ∑}
ΔV_VSET
C_B2 should be 10× to 20× C_B1 to divide the ripple voltage
present at the charger output. Therefore C_B1 = 0.01μF and
C_B2 = 0.1μF are good starting values. In order to prevent
overshoot during start-up transients the time constant as-
sociated with C_B2 must be shorter than the time constant
of C5 at the I_TH pin. If C_B2 is increased to improve ripple
rejection, then C5 should be increased proportionally and
charger response time to voltage variation will degrade.
Input and Output Capacitors
In the 4A Lithium Battery Charger (Typical Application
section), the input capacitor (C_IN) is assumed to absorb all
input switching ripple current in the converter, so it must
have adequate ripple current rating. Worst-case RMS ripple
current will be equal to one half of output charging current.
Actual capacitance value is not critical. Solid tantalum
low ESR capacitors have high ripple current rating in a
relatively small surface mount package, but caution must
be used when tantalum capacitors are used for input or
output bypass. High input surge currents can be created
when the adapter is hot-plugged to the charger or when a
battery is connected to the charger. Solid tantalum capaci-
tors have a known failure mechanism when subjected to
very high turn-on surge currents. Only Kemet T495 series
of “Surge Robust” low ESR tantalums are rated for high
surge conditions such as battery to ground.
1760fa
40