LTC2911_15 Datasheet, PDF (4/20 Pages) Linear Technology – Precision Triple Supply Monitor with Power-Fail Comparator

LTC2911
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. V_ADJ = 0.55V, V_PFI = 0.55V, V1 = 3.3V unless otherwise noted. (Notes 2, 3)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
t_P,PF
PFI Comparator Propagation Delay to PFO
V_PFI Driven Beyond Threshold l
8
30
80
µs
V_PFT by More Than 10%
t_UV
V1, V2, ADJ Undervoltage Detect to RST Low
V_X Less Than Threshold V_RTX by l
8
30
80
µs
More Than 10%
V_OH
RST, PFO Output Voltage High (Note 5)
I_RST = –1µA
l V1 – 1
V1
V
V_OL
RST, PFO Output Voltage Low (Note 6)
V_CC = 0.5V, I = 5µA
l
V_CC = 1V, I = 100µA
l
V_CC = 3V, I = 2.5mA
l
0.01
0.15
V
0.01
0.15
V
0.10
0.30
V
t_RST(EXT)
Reset Timeout Period, External
C_TMR = 2.2nF
l
15
20
27
ms
t_RST(INT)
Reset Timeout Period, Internal
V_TMR = V1
l 140
200
280
ms
V_TMR(INT) Timer Internal Mode Threshold
V_TMR Rising
l V1 – 0.40 V1 – 0.020 V1 – 0.10
V
∆V_TMR(INT) Timer Internal Mode Hysteresis
V_TMR Falling
l
40
100
160
mV
V_TMR(LATCH) Timer Latch Mode Threshold
V_TMR Falling
l 0.10
0.20
0.40
V
∆V_TMR(LATCH) Timer Latch Mode Hysteresis
V_TMR Rising
l
40
75
160
mV
t_P, LR
Latch Release Propagation Delay to RST Low
V_TMR Rising, Step 0V to 0.6V
l
0.5
3
µs
t_SU,MON
Monitor Input Setup Time to Latch Enable (Note 7) V_TMR Falling, Step 0.6V to 0V
l
2
ms
Monitor Input Setup Time to Latch Release
V_TMR Rising, Step 0V to 0.6V
t_{HD, MON}
Monitor Input Hold Time to Latch Enable
V_TMR Falling, Step 0.6V to 0V
l
0
µs
Monitor Input Hold Time to Latch Release
V_TMR Rising, Step 0V to 0.6V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.
Note 3: The internal supply voltage (V_CC) is generated from the greater of
the voltages on the V1 and V2 inputs. V_CC = V1 for the LTC2911-5.
Note 4: Under typical operating conditions, quiescent current is drawn
from the greater of the voltages on the V1 and V2 inputs. For the
LTC2911‑5 only V1 supplies the quiescent current.
Note 5: The RST and PFO output pins on the LTC2911 have internal pull-
ups to V1. However, for faster rise times or for V_OH voltages greater than
V1, use an external pull-up resistor.
Note 6: The RST and PFO pull-down currents are derived from V1 and V2
except for the LTC2911-5 where the pull-down strength is derived only
from V1.
Note 7: t_SU,MON is required to latch a low RST state and t_SU,MON + t_RST is
required to latch a high RST state.
2911f
4