LTC2495 Datasheet, PDF (4/32 Pages) Linear Technology – 16-Bit 8-/16-Channel ΔΣ ADC with PGA, Easy Drive and I2C Interface

LTC2495
ANALOG INPUT AND REFERENCE The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. (Note 3)
SYMBOL
IN⁺
IN^–
V_IN
FS
LSB
REF⁺
REF^–
V_REF
CS(IN⁺)
CS(IN^–)
PARAMETER
CONDITIONS
Absolute/Common Mode IN⁺ Voltage
(IN⁺ Corresponds to the Selected Positive Input Channel)
Absolute/Common Mode IN^– Voltage
(IN^– Corresponds to the Selected Negative Input Channel)
Input Differential Voltage Range (IN⁺ – IN^–)
Full Scale of the Differential Input (IN⁺ – IN^–)
Least Significant Bit of the Output Code
Absolute/Common Mode REF⁺ Voltage
Absolute/Common Mode REF^– Voltage
Reference Voltage Range (REF⁺ – REF^–)
IN⁺ Sampling Capacitance
IN^– Sampling Capacitance
MIN
GND – 0.3V
TYP
MAX
V_CC + 0.3V
UNITS
V
GND – 0.3V
V_CC + 0.3V
V
●
–FS
+FS
V
● 0.5V_REF/Gain
V
●
FS/2¹⁶
●
0.1
●
GND
V_CC
V
REF⁺ – 0.1V
V
●
0.1
V_CC
V
11
pF
11
pF
CS(V_REF)
I_{DC_LEAK(IN+)}
I_{DC_LEAK(IN–)}
I_{DC_LEAK(REF+)}
I_{DC_LEAK(REF–)}
t_OPEN
QIRR
V_REF Sampling Capacitance
IN⁺ DC Leakage Current
IN^– DC Leakage Current
REF⁺ DC Leakage Current
REF^– DC Leakage Current
MUX Break-Before-Make
MUX Off Isolation
11
pF
Sleep Mode, IN⁺ = GND ●
–10
1
10
nA
Sleep Mode, IN^– = GND ●
–10
1
10
nA
Sleep Mode, REF⁺ = V_CC ●
–100
1
100
nA
Sleep Mode, REF^– = GND ●
–100
1
100
nA
50
ns
V_IN = 2V_P-P DC to 1.8MHz
120
dB
I²C INPUTS AND DIGITAL OUTPUTS _{The ● denotes the specifications which apply over the full}
operating temperature range, otherwise specifications are at T_A = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
V_IH
High Level Input Voltage
V_IL
Low Level Input Voltage
V_IHA
Low Level Input Voltage for Address Pins CA0, CA1, CA2
V_ILA
High Level Input Voltage for Address Pins CA0, CA1, CA2
R_INH
Resistance from CA0, CA1, CA2 to V_CC to Set Chip
Address Bit to 1
● 0.7V_CC
●
●
● 0.95V_CC
●
0.3V_CC
0.05V_CC
10
R_INL
Resistance from CA0, CA1, CA2 to GND to Set Chip
Address Bit to 0
●
10
R_INF
Resistance from CA0, CA1, CA2 to GND or V_CC to Set
Chip Address Bit to Float
●
2
I_I
Digital Input Current (F_O)
V_HYS
Hysteresis of Schmitt Trigger Inputs
V_OL
Low Level Output Voltage (SDA)
t_OF
Output Fall Time V_IH(MIN) to V_IL(MAX)
● –10
10
(Note 5)
● 0.05V_CC
I = 3mA
●
0.4
Bus Load C_B 10pF to
● 20 + 0.1C_B
250
400pF (Note 14)
I_IN
Input Leakage (SDA/SCL)
0.1V_CC ≤ V_IN ≤ 0.9 • V_CC ●
1
C_CAX
External Capacitative Load on Chip Address Pins (CA0,
●
10
CA1, CA2) for Valid Float
UNITS
V
V
V
V
kΩ
kΩ
MΩ
µA
V
V
ns
µA
pF
2495f
4