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LTC2226H Datasheet, PDF (4/16 Pages) Linear Technology – 12-Bit, 25Msps 125°C ADC in LQFP
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LTC2226H
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
LOGIC OUTPUTS
OVDD = 3V
COZ
ISOURCE
ISINK
VOH
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
High Level Output Voltage
VOL
Low Level Output Voltage
OVDD = 2.5V
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
OVDD = 1.8V
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
OE = High (Note 7)
VOUT = 0V
VOUT = 3V
IO = –10μA
IO = –200μA
IO = 10μA
IO = 1.6mA
IO = –200μA
IO = 1.6mA
IO = –200μA
IO = 1.6mA
3
pF
50
mA
50
mA
2.995
V
l 2.7
2.99
V
0.005
V
l
0.09
0.4
V
2.49
V
0.09
V
1.79
V
0.09
V
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VDD
OVDD
IVDD
PDISS
PSHDN
PNAP
Analog Supply Voltage
Output Supply Voltage
Supply Current
Power Dissipation
Shutdown Power
Nap Mode Power
(Note 9)
(Note 9)
SHDN = H, OE = H, No CLK
SHDN = H, OE = L, No CLK
l 2.8
3
3.5
V
l 0.5
3
3.6
V
l
25
30
mA
l
75
90
mW
2
mW
15
mW
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fS
Sampling Frequency
tL
CLK Low Time
(Note 9)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
l
1
25
MHz
l 18.9
20
500
ns
l
5
20
500
ns
tH
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
l 18.9
20
500
ns
l
5
20
500
ns
tAP
Sample-and-Hold Aperture Delay
tD
CLK to DATA Delay
Data Access Time After OE↓
BUS Relinquish Time
CL = 5pF (Note 7)
CL = 5pF (Note 7)
(Note 7)
0
ns
l 1.4
2.7
6
ns
l
4.3
12
ns
l
3.3
10
ns
Pipeline Latency
5
Cycles
2226hfb
4
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