LT1028 Datasheet, PDF (4/20 Pages) Linear Technology – Ultra Low Noise Precision High Speed Op Amps

LT1028/LT1128
ELECTRICAL CHARACTERISTICS V_S = ±15V, 0°C ≤ T_A ≤ 70°C, unless otherwise noted.
SYMBOL PARAMETER
V_OS
∆V_OS
∆Temp
Input Offset Voltage
Average Input Offset Drift
I_OS
Input Offset Current
I_B
Input Bias Current
Input Voltage Range
CMRR Common-Mode Rejection Ratio
PSRR Power Supply Rejection Ratio
A_VOL Large-Signal Voltage Gain
V_OUT Maximum Output Voltage Swing
I_S
Supply Current
CONDITIONS
(Note 1)
(Note7)
V_CM = 0V
V_CM = 0V
V_CM = ±10.5V
V_S = ±4.5V to ±18V
R_L ≥ 2k, V_O = ±10V
R_L ≥ 1k, V_O = ±10V
R_L ≥ 2k
R_L ≥ 600Ω (Note 9)
LT1028AC
LT1128AC
MIN TYP MAX
q
15 80
q
0.1 0.8
LT1028C
LT1128C
MIN TYP MAX
30 125
0.2 1.0
q
15 65
q
±30 ±120
q ±10.5 ±12.0
q 110 124
q 114 132
q 5.0 25.0
4.0 18.0
q ±11.5 ±12.7
±9.5 ±11.0
q
8.0 10.5
±10.5
106
107
3.0
2.5
±11.5
±9.0
22
±40
±12.0
124
132
25.0
18.0
±12.7
±10.5
8.2
130
±240
11.5
UNITS
µV
µV/ °C
nA
nA
V
dB
dB
V/µV
V/µV
V
V
mA
ELECTRICAL CHARACTERISTICS V_S = ±15V, –40°C ≤ T_A ≤ 85°C, unless otherwise noted. (Note 10)
SYMBOL PARAMETER
V_OS
∆V_OS
∆Temp
Input Offset Voltage
Average Input Offset Drift
I_OS
Input Offset Current
I_B
Input Bias Current
Input Voltage Range
CMRR Common-Mode Rejection Ratio
PSRR Power Supply Rejection Ratio
A_VOL Large-Signal Voltage Gain
V_OUT Maximum Output Voltage Swing
I_S
Supply Current
CONDITIONS
V_CM = 0V
V_CM = 0V
V_CM = ±10.5V
V_S = ±4.5V to ±18V
R_L ≥ 2k, V_O = ±10V
R_L ≥ 1k, V_O = ±10V
R_L ≥ 2k
LT1028AC
LT1128AC
MIN TYP MAX
q
20 95
q
0.2 0.8
LT1028C
LT1128C
MIN TYP MAX
35 150
0.25 1.0
q
20 80
q
±35 ±140
q ±10.4 ±11.8
q 108 123
q 112 131
q 4.0 20.0
3.0 14.0
q ±11.0 ±12.5
q
8.5 11.0
±10.4
102
106
2.5
2.0
±11.0
28
±45
±11.8
123
131
20.0
14.0
±12.5
8.7
160
±280
12.5
UNITS
µV
µV/°C
nA
nA
V
dB
dB
V/µV
V/µV
V
mA
The q denotes specifications which apply over the full operating
temperature range.
Note 1: Input Offset Voltage measurements are performed by automatic
test equipment approximately 0.5 sec. after application of power. In
addition, at T_A = 25°C, offset voltage is measured with the chip heated to
approximately 55°C to account for the chip temperature rise when the
device is fully warmed up.
Note 2: Long Term Input Offset Voltage Stability refers to the average
trend line of Offset Voltage vs. Time over extended periods after the first
30 days of operation. Excluding the initial hour of operation, changes in
V_OS during the first 30 days are typically 2.5µV.
Note 3: This parameter is tested on a sample basis only.
Note 4: 10Hz noise voltage density is sample tested on every lot with the
exception of the S8 and S16 packages. Devices 100% tested at 10Hz are
available on request.
Note 5: Current noise is defined and measured with balanced source
resistors. The resultant voltage noise (after subtracting the resistor noise
on an RMS basis) is divided by the sum of the two source resistors to
obtain current noise. Maximum 10Hz current noise can be inferred from
100% testing at 1kHz.
Note 6: Gain-bandwidth product is not tested. It is guaranteed by design
and by inference from the slew rate measurement.
Note 7: This parameter is not 100% tested.
Note 8: The inputs are protected by back-to-back diodes. Current-limiting
resistors are not used in order to achieve low noise. If differential input
voltage exceeds ±1.8V, the input current should be limited to 25mA.
Note 9: This parameter guaranteed by design, fully warmed up at T_A =
70°C. It includes chip temperature increase due to supply and load
currents.
Note 10: The LT1028/LT1128 are not tested and are not quality-
assurance-sampled at –40°C and at 85°C. These specifications are
guaranteed by design, correlation and/or inference from –55°C, 0°C, 25°C,
70°C and /or 125°C tests.
4