LTC2185_15 Datasheet, PDF (35/36 Pages) Linear Technology – 16-Bit, 125/105/80Msps Low Power Dual ADCs

LTC2185/LTC2184/LTC2183
Package Description
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
0.70 ±0.05
7.15 ±0.05
7.50 REF
(4 SIDES)
8.10 ±0.05 9.50 ±0.05
7.15 ±0.05
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
9 .00 ± 0.10
(4 SIDES)
PIN 1 TOP MARK
(SEE NOTE 5)
PACKAGE OUTLINE
0.75 ± 0.05
R = 0.10
TYP
7.50 REF
(4-SIDES)
R = 0.115
TYP
7.15 ± 0.10
63 64
PIN 1
CHAMFER
C = 0.35
0.40 ± 0.10
1
2
7.15 ± 0.10
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
(UP64) QFN 0406 REV C
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
218543f
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