LT8710_15 Datasheet, PDF (34/44 Pages) Linear Technology – Synchronous SEPIC/ Inverting/Boost Controller with Output Current Control

LT8710
AppENDIX
current. At the same time, choose MOSFETs with a lower
total gate charge to reduce LT8710 power dissipation and
MOSFET switching losses.
The turn-off delay time (t_D(OFF)) of available NFETs is
generally smaller than the LT8710’s non-overlap time.
However, the turn-off time of the available PFETs should
be looked at before deciding on a PFET for a given applica-
tion. The turn-off time must be less than the non-overlap
time of the LT8710 or else the NFET and PFET could be
on at the same time and damage to external components
may occur. If the PFET turn-off delay time as specified in
the data sheet is less than the LT8710 non-overlap time,
then the PFET is good to use. If the turn-off delay time is
longer than the non-overlap time, it doesn’t necessarily
mean it can’t be used. It may be unclear how the PFET
manufacturer measures the turn-off delay time, so it is
best to measure the PFET turn-off delay time with respect
to the PFET gate voltage.
Finally, both the NFET and PFET power MOSFETs should
be in a package with an exposed paddle for the drain
connection to be able to dissipate heat. The on-resistance
of MOSFETs is proportional to temperature, so it’s more
efficient if the MOSFETs are running cool with the help
of the exposed paddle. See Table 6 for a list of power
MOSFET manufacturers.
Table 6. Power MOSFET (NFET and PFET) Manufacturers
Fairchild Semiconductor www.fairchildsemi.com
On-Semiconductor
www.onsemi.com
Vishay
www.vishay.com
Diodes Inc.
www.diodes.com
INPUT AND OUTPUT CAPACITOR SELECTION
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out of the regulator. A parallel combination of ca-
pacitors is typically used to achieve high capacitance and
low ESR (equivalent series resistance). Tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
noise. A minimum 1µF ceramic capacitor should also be
placed from V_IN to GND and from BIAS to GND as close
to the LT8710 pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce ripple voltage and help reduce power loss in the
higher ESR bulk capacitors. X5R or X7R dielectrics are
preferred, as these materials retain their capacitance over
wide voltage and temperature ranges. Many ceramic ca-
pacitors, particularly 0805 or 0603 case sizes, have greatly
reduced capacitance at the desired operating voltage.
Input Capacitor, C_IN
The input capacitor, C_IN, sees the ripple current of the input
inductor, L₁, which eases the capacitance requirements of
C_IN. Below is the equation for calculating the capacitance
of C_IN for 0.5% input voltage ripple:
C_IN
>
8
•L
•
DC
f² • 0.005
where:
DC = Switch duty cycle (see Power Switch Duty Cycle
section)
L = L_BOOST or L_DUAL (see Inductor Selection section)
f = Switching frequency
The worst-case for the input capacitor (largest capacitance
needed) is when the input voltage is at its lowest because
the duty cycle is the highest. Keep in mind that the volt-
age rating of the input capacitor needs to be greater than
the maximum input voltage. This equation calculates the
capacitance value during steady-state operation and may
need to be adjusted for desired transient response. Also,
this assumes no ESR, so the input capacitance may need
to be larger depending on the equivalent ESR of the input
capacitor(s).
Output Capacitor, C_OUT
The output capacitor, C_OUT, in a boost or SEPIC topology
has chopped current flowing through it, whereas the output
capacitor in a dual inductor inverting topology sees the
8710f
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