LTC4269-1 Datasheet, PDF (32/44 Pages) Linear Technology – IEEE 802.3at PD with Synchronous No-Opto Flyback Controller

LTC4269-1
APPLICATIONS INFORMATION
The LTC4269-1 has an internal clamp on V_CC of approxi-
mately 19.5V. This provides some protection for the part
in the event that the switcher is off (UVLO low) and the
V_CC node is pulled high. If R_TR is sized correctly, the part
should never attain this clamp voltage.
Control Loop Compensation
Loop frequency compensation is performed by connect-
ing a capacitor network from the output of the feedback
amplifier (V_CMP pin) to ground as shown in Figure 15.
Because of the sampling behavior of the feedback amplifier,
compensation is different from traditional current mode
controllers. Normally only C_VCMP is required. R_VCMP can
be used to add a zero, but the phase margin improvement
traditionally offered by this extra resistor is usually already
accomplished by the nonzero secondary circuit impedance.
C_VCMP2 can be used to add an additional high frequency
pole and is usually sized at 0.1 times C_VCMP.
V_CMP
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C_VCMP2
R_VCMP
C_VCMP
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Figure 15. V_CMP Compensation Network
In further contrast to traditional current mode switchers,
V_CMP pin ripple is generally not an issue with the LTC4269-1.
The dynamic nature of the clamped feedback amplifier
forms an effective track/hold type response, whereby the
V_CMP voltage changes during the flyback pulse, but is then
held during the subsequent switch-on portion of the next
cycle. This action naturally holds the V_CMP voltage stable
during the current comparator sense action (current mode
switching).
Application Note 19 provides a method for empirically
tweaking frequency compensation. Basically, it involves
introducing a load current step and monitoring the
response.
Slope Compensation
The LTC4269-1 incorporates current slope compensation.
Slope compensation is required to ensure current loop
stability when the DC is greater than 50%. In some switching
regulators, slope compensation reduces the maximum peak
current at higher duty cycles. The LTC4269-1 eliminates
this problem by having circuitry that compensates for
the slope compensation so that maximum current sense
voltage is constant across all duty cycles.
Minimum Load Considerations
At light loads, the LTC4269-1 derived regulator goes into
forced continuous conduction mode. The primary-side
switch always turns on for a short time as set by the
t_ON(MIN) resistor. If this produces more power than the
load requires, power will flow back into the primary dur-
ing the off period when the synchronization switch is on.
This does not produce any inherently adverse problems,
although light load efficiency is reduced.
Maximum Load Considerations
The current mode control uses the V_CMP node voltage
and amplified sense resistor voltage as inputs to the
current comparator. When the amplified sense voltage
exceeds the V_CMP node voltage, the primary-side switch
is turned off.
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
V_CMP reaches its 2.56V clamp. At clamp, the primary-side
MOSFET will turn off at the rated 100mV V_SENSE level. This
repeats on the next cycle.
It is possible for the peak primary switch currents as
referred across R_SENSE to exceed the max 100mV rating
because of the minimum switch on time blanking. If the
voltage on V_SENSE exceeds 205mV after the minimum
turn-on time, the SFST capacitor is discharged, causing
the discharge of the V_CMP capacitor. This then reduces
the peak current on the next cycle and will reduce overall
stress in the primary switch.
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