LTC1760_1 Datasheet, PDF (32/44 Pages) Linear Technology – Dual Smart Battery System Manager

LTC1760
U
OPERATIO
V_PLUS and 2µF on V_CC, including tolerances) should keep
the LTC1760 operating above the UVLO trip voltage long
enough to perform the short-circuit function when the
input voltages are greater than 8V. Increasing the capaci-
tor across V_CC to 4.7µF will allow operation down to the
recommended 6V minimum.
8.3 Emergency Turn-Off
All of the PowerPath switches can be forced off by setting
the DCDIV pin to a voltage between 8V and 10V. This will
have the same effect as a short-circuit event. DCDIV must
be less than 5V and V_PLUS must decrease below the UVLO
threshold to re-enable the PowerPath switches. The
LTC1760 can recover from this condition without remov-
ing power. Contact Applications Engineering for more
information.
8.4 Power-Up Strategy
All three PowerPath switches are turned on after V_PLUS
exceeds the UVLO threshold for more than 250ms. This
delay is to prevent oscillation from a turn-on transient near
the UVLO threshold.
9 The Voltage DAC Block
The voltage DAC (VDAC) is a delta-sigma modulator which
controls the effective value of an internal resistor,
R_VSET = 7.2k, used to program the maximum charger
voltage. Figure 7 is a simplified diagram of the VDAC
operation. The delta-sigma modulator and switch SWV
convert the VDAC value to a variable resistance equal to
(11/8)R_VSET/(VDAC_(VALUE)/2047). In regulation, V_SET is
servo driven to the 0.8V reference voltage, V_REF.
CSN
C_B2
V_SET
C_B1
R_VF
405.3k
V_REF
R_VSET
7.2k
–
EA
+
SWV
∆Σ
11
MODULATOR
TO
I_TH
DAC
VALUE
(11 BITS)
1760 F07
Figure 7. Voltage DAC Operation
Capacitors C_B1 and C_B2 are used to average the voltage
present at the V_SET pin as well as provide a zero in the
voltage loop to help stability and transient response time
to voltage variations.
10 The Current DAC Block
The current DAC is a delta-sigma modulator which
controls the effective value of an internal resistor,
R_SET = 18.77k, used to program the maximum charger
current. Figure 8 is a simplified diagram of the DAC opera-
tion. The delta-sigma modulator and switch convert the
IDAC value to a variable resistance equal to 1.25R_SET/
(IDAC_(VALUE)/1023). In regulation, I_SET is servo driven to
the 0.8V reference voltage, V_REF, and the current from R_SET
is matched against a current derived from the voltage
between pins CSP and CSN. This current is (V_CSP – V_CSN)/
3k.
Therefore programmed current is:
I_CHG = 0.8 V_REF 3k/(R_SNS R_SET) • (IDAC_(VALUE)/1023)
= (102.3mV/R_SNS) • (IDAC_(VALUE)/1023)
During wake-up current operation, the current DAC enters
a low current mode. The current DAC output is pulse-width
modulated with a high frequency clock having a duty cycle
value of 1/8. Therefore, the maximum output current pro-
vided by the charger is I_MAX/8. The delta-sigma output gates
this low duty cycle signal on and off. The delta-sigma shift
registers are then clocked at a slower rate, about 40ms/bit,
so that the charger has time to settle to the I_MAX/8 value.
(V_CSP – V_CSN)
3kΩ
(FROM CA1 AMPLIFIER)
I_SET
+
C_SET
V_{REF –}
R_SET
18.77k
∆Σ
10
MODULATOR
Figure 8. Current Dac Operation
TO
I_TH
DAC
VALUE
(10 BITS)
1760 F08
1760f
32