LTC2273 Datasheet, PDF (30/44 Pages) Linear Technology – 16-Bit, 80Msps/65Msps Serial Output ADC

LTC2273/LTC2272
APPLICATIONS INFORMATION
START
WAIT FOR NEXT
FRAME CLOCK
NO
SYNC
YES
REQUEST?
DATA TRANSMISSION
FLOW (SEE FIGURE 18)
NO
IS ISMODE
ENABLED?
YES
TRANSMIT K28.5
AS CODE GROUP 1
NO _NEGATIVE YES
DISPARITY?
TRANSMIT K28.5
AS CODE GROUP 2
(DISPARITY NOT OK)
(DISPARITY IS OK)
TRANSMIT K28.5
AS CODE GROUP 1
TRANSMIT K28.5
AS CODE GROUP 1
(NEGATIVE DISPARITY)
(POSITIVE DISPARITY)
TRANSMIT D5.6
AS CODE GROUP 2
TRANSMIT D16.2
AS CODE GROUP 2
(NEGATIVE DISPARITY)
(NEGATIVE DISPARITY)
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Figure 15. Initial Synchronization Flow Diagram
Scrambling
To avoid spectral interference from the serial data output,
an optional data scrambler is added between the ADC
data and the 8B/10B encoder to randomize the spectrum
of the serial link. The scrambler is enabled by setting the
SCRAM pin to a high logic level. The polynomial used for
the scrambler is 1 + x¹⁴ + x¹⁵, which is a pseudo-random
pattern repeating itself every 2¹⁵–1. Figure 16 illustrates
the LTC2273/LTC2272 implementation of this polynomial
in parallel form.
The scrambled data is converted into two valid 8B/10B
code groups, constituting a complete frame. The 8B/10B
code groups are then serialized and transmitted.
The receiver is required to deserializing the data, decode
the code-groups into octets and descramble them back
to the original octets using the self-aligning descrambler
shown in Figure 17. This descrambler is shown in 16-bit
parallel form, which is an efficient implementation of the
(1 + x¹⁴ + x¹⁵) polynomial, operating at the frame clock
rate (ADC sample rate).
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