LT3752-1_15 Datasheet, PDF (30/52 Pages) Linear Technology – Active Clamp Synchronous Forward Controllers with Internal Housekeeping Controller

LT3752/LT3752-1
APPLICATIONS INFORMATION
cally 0.75 but may be further limited by the transformer
design and voltage ratings of components connected to
the drain of the primary side power MOSFET (SWP). See
voltage calculations in the LO side and HI side active clamp
topologies sections.
If system input voltage falls below it's UVLO threshold
the part will enter soft-stop with continued switching.
The LT3752/LT3752-1 include an intelligent circuit which
prevents D_VSEC from continuing to rise as system input
voltage falls (see Soft-Stop). Without this, too large a D_VSEC
would require extremely high reset voltages on the SWP
node to properly reset the transformer. The UVLO_V_SEC
pin maximum operational level is the lesser of V_IN – 2V
or 12.5V.
The LT3752/LT3752-1 volt-second clamp architecture
is superior to an external RC network connected from
system input to trip an internal comparator threshold.
The RC method suffers from external capacitor error, part-
to-part mismatch between the RC time constant and the
IC’s switching period, the error of the internal comparator
threshold and the nonlinearity of charging at low input
voltages. The LT3752/LT3752-1 use the R_IVSEC resistor to
define the charge current for an internal timer capacitor to
set an OUT pin maximum on-time, t_ON(VSEC). The voltage
across R_IVSEC follows UVLO_V_SEC pin voltage (divided
down from system input voltage). Hence, R_IVSEC current
varies linearly with input supply. The LT3752/LT3752-1
also trim out internal timing capacitor and comparator
threshold errors to optimize part-to-part matching between
t_ON(VSEC) and T.
D_VSEC Open Loop Control: No Opto-Coupler, Error
Amplifier or Reference
The accuracy of the programmable volt-second clamp
(D_VSEC) safely controls V_OUT if open loop conditions exist
such as no opto-coupler, error amplifier or reference on the
secondary side. D_VSEC controls the output of the converter
by controlling duty cycle inversely proportional to system
input. If D_VSEC duty cycle guardrail is programmed X%
above natural duty cycle, V_OUT will only increase by X%
if a closed loop system breaks open. This volt-second
clamp is operational over a 10:1 system input voltage
range. See D_VSEC versus UVLO_V_SEC pin voltage in the
Typical Performance Characteristics section.
R_IVSEC: Open Pin Detection Provides Safety
The LT3752/LT3752-1 provide an open-detection safety
feature for the R_IVSEC pin. If the R_IVSEC resistor goes
open circuit the part immediately stops switching. This
prevents the part from running without the volt-second
clamp in place.
Transformer Reset: Active Clamp Technique
The LT3752/LT3752-1 include a ±0.4A gate driver at the
AOUT pin to allow the use of an active clamp transformer
reset technique (Figures 13, 17). The active clamp method
improves efficiency and reduces voltage stress on the
main power switch, M1. By switching in the active clamp
capacitor only when needed, the capacitor does not lose
its charge during M1 on-time. By allowing the active clamp
capacitor, C_CL, to store the average voltage required to
reset the transformer, the main power switch sees lower
drain voltage.
An imbalance of volt-seconds will cause magnetizing cur-
rent to walk upwards or downwards until the active clamp
capacitor is charged to the optimal voltage for proper
transformer reset. The voltage rating of the capacitor will
depend on whether the active clamp capacitor is actively
switched to ground (Figure 13) or actively switched to
30
For more information www.linear.com/LT3752
3752fb