LTC4308_15 Datasheet, PDF (3/16 Pages) Linear Technology – Low Voltage, Level Shifting Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery

LTC4308
ELECTRICAL CHARACTERISTICS _{The l denotes the specifications which apply over the full operating}
temperature range, otherwise specifications are at T_A = 25°C. V_CC = 3.3V, unless otherwise noted.
SYMBOL
PARAMETER
t_IDLE
V_{THR_EN}
Bus Idle Time
ENABLE Threshold Voltage
V_{THR_EN(HYST)}
I_ENABLE
t_{PLH_EN}
t_{PHL_EN}
t_{PLH_READY}
ENABLE Threshold Voltage Hysteresis
ENABLE Input Current
ENABLE Delay Off-On
ENABLE Delay On-Off
READY Delay Off-On
t_{PHL_READY} READY Delay On-Off
V_{OL_READY}
READY Output Low Voltage
I_{OFF_READY}
READY Off Leakage Current
Prop Delay and Rise-Time Accelerators
CONDITIONS
ENABLE Rising Edge
(Note 3)
ENABLE from 0V to V_CC
(Figure 1)
(Note 3), (Figure 1)
(Note 3), (Figure 1)
(Note 3), (Figure 1)
I_READY = 3mA, V_CC = 2.3V
V_CC = READY = 5.5V
MIN TYP MAX UNITS
l 55 95 175
μs
l 0.45 0.6 0.75
V
35
mV
l
0.1 ±5
μA
95
μs
10
ns
10
ns
10
ns
l
0.4
V
l
0.1 ±5
μA
t_PHL
SDA/SCL Propagation Delay High to Low
t_PLH
SDA/SCL Propagation Delay Low to High
t_RISE
SDA/SCL Transition Time Low to High
t_FALL
SDA/SCL Transition Time High to Low
I_PULLUPAC
Transient Boosted Pull-Up Current
Input-Output Connection
C_LOAD = 50pF, 2.7k to V_CC on SDA, SCL,
(Notes 2, 3), (Figure 1)
C_LOAD = 50pF, 2.7k to V_CC on SDA, SCL,
(Notes 2, 3), (Figure 1)
C_LOAD = 100pF, 10k to V_CC on SDA, SCL,
(Notes 3, 4), (Figure 1)
C_LOAD = 100pF, 10k to V_CC on SDA, SCL,
(Notes 3, 4), (Figure 1)
Positive Transition > 0.8V/μs on SDAOUT,
SCLOUT (Note 5)
70
ns
10
ns
30 300
ns
30 300
ns
5
8
mA
V_OS
Input to Output Offset Voltage (OUT – IN)
2.7k to V_CC on SDAOUT, SCLOUT,
SDAIN = SCLIN = 0.2V
l 250 300 380 mV
Output to Input Offset Voltage (IN – OUT)
2.7k to V_CC on SDAOUT, SCLOUT,
SDAIN = SCLIN = 0.4V, V_CC = 5.5V
2.7k to V_CC on SDAIN, SCLIN,
SDAOUT = SCLOUT = 0.4V
l 250 350 450 mV
l –150 –200 –300 mV
2.7k to V_CC on SDAIN, SCLIN,
SDAOUT = SCLOUT = 0.4V, V_CC = 5.5V
l –150 –250 –350 mV
V_THR
SDAOUT, SCLOUT Logic Input Threshold Voltage V_CC ≥ 2.9V
V_CC < 2.9V
1.4 1.65 1.9
V
1.1 1.35 1.6
V
SDAIN, SCLIN Logic Input Threshold Voltage SDAIN, SCLIN Rising Edge, V_CC = 2.3V, 5.5V
0.45 0.6 0.75
V
V_THR(HYST)
C_IN
I_LEAK
V_OL
V_ILMAX
SDAOUT, SCLOUT Logic Input Threshold Voltage (Note 3)
Hysteresis
SDAIN, SCLIN Logic Input Threshold Voltage
Hysteresis
(Note 3)
Digital Input Capacitance SDAIN, SDAOUT,
SCLIN, SCLOUT
(Note 3)
Input Leakage Current
SDA, SCL Pins
Output Low Voltage
SDAOUT, SCLOUT Pins, I_SINK = 4mA,
SDAIN = SCLIN = 0V, V_CC = 2.7V
2.7k to V_CC on SDAOUT, SCLOUT,
SDAIN = SCLIN = 0V
Buffer Input Logic Low Voltage
SDAOUT, SCLOUT Pins
50
mV
35
mV
10
pF
l
l0
±5
μA
400 mV
l 250 300 380 mV
l
1.2
V
4308f
3