LTC4265 Datasheet, PDF (3/20 Pages) Linear Technology – IEEE 802.3at High Power PD Interface Controller with 2-Event Classifi cation Recognition

LTC4265
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C.
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Operating Input Voltage
Signature Range
Classification Range
Turn-On Voltage
Undervoltage Lock Out
Overvoltage Lock Out
At GND Pin (Note 5)
60
V
l 1.5
9.8
V
l 12.5
21
V
l
37.2
V
l 30.0
V
71
V
ON/UVLO Hysteresis Window
l 4.1
V
Signature/Class Hysteresis Window
l 1.4
V
Reset Threshold
State Machine Reset for 2-event Classification
l 2.57
5.40
V
SUPPLY CURRENT
Supply Current at 60V
Measured at GND Pin
l
1.35
mA
Class 0 Current
SIGNATURE
GND = 17.5V, No R_CLASS Resistor
l
0.40
mA
Signature Resistance
1.5V ≤ GND ≤ 9.8V (Note 6)
l 23.25
26
kΩ
Invalid Signature Resistance, SHDN Invoked 1.5V ≤ GND ≤ 9.8V, V_SHDN = 3V (Note 6)
l
Invalid Signature Resistance During Mark Event (Notes 6, 7)
l
11
kΩ
11
kΩ
CLASSIFICATION
Class Accuracy
Classification Stability Time
10mA < I_CLASS < 40mA, 12.5V < GND < 21V (Note 8, 9) l
GND Pin Step to 17.5V, R_CLASS = 30.9, I_CLASS Within
l
3.5% of Ideal Value (Notes 8, 9)
±3.5
%
1
ms
NORMAL OPERATION
Inrush Current
GND = 54, V_OUT = 3V
l 60
100
180
mA
Power FET On Resistance
Power FET Leakage Current at V_OUT
DIGITAL INTERFACE
Tested at 600mA into V_OUT, GND = 54V
GND = SHDN = V_OUT = 57V
l
0.70
1.0
Ω
l
1
μA
SHDN Input High Level Voltage
l
3
V
SHDN Input Low Level Voltage
l
0.45
V
SHDN Input Resistance
PWRGD, T2PSE Voltage Output Low
PWRGD, T2PSE Leakage Current
PWRGD Voltage Output Low
PWRGD Voltage Clamp
PWRGD Leakage Current
GND = 9.8V, SHDN = 9.65V
l 100
Tested at 1mA, GND = 54V. For T2PSE, Must Complete l
2-event Classification to See Active Low.
Pin Voltage Pulled 57V, GND = V_IN = 0
l
Tested at 0.5mA, GND = 52V, V_OUT = 48V, Output Voltage l
is with Respect to V_OUT
Tested at 2mA, V_OUT = 0V, Voltage with Respect to V_OUT l 12
V_PWRGD = 11V, V_OUT = V_IN = 0V, GND = 54V
l
kΩ
0.15
V
1
μA
0.4
V
16.5
V
1
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All voltages are with respect to V_IN pin unless otherwise noted.
Note 3: Pins with 100V absolute maximum guaranteed for T ≥ 0ºC, otherwise 90V.
Note 4: PWRGD voltage clamps at 14V with respect to V_OUT.
Note 5: Input voltage specifications are defined with respect to LTC4265
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
Note 6: Signature resistance is measured via the ΔV/ΔI method with a
minimum ΔV of 1V. The LTC4265 signature resistance accounts for the
additional series resistance in the input diode bridge.
Note 7: An invalid signature after the 1st classification event is mandated
by IEEE 802.3at standard. See Applications Information.
Note 8: Class accuracy is with respect to the ideal current defined as
1.237/R_CLASS and does not include variations in R_CLASS resistance.
Note 9: This parameter is assured by design and wafer level testing.
4265f
3