LTC4264_15 Datasheet, PDF (3/24 Pages) Linear Technology – High Power PD Interface Controller with 750mA Current Limit

LTC4264
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
V_{IL_ILIM}
I_{LIM_EN} Low Level Input Voltage
With Respect to V_IN (Note 13)
●
V_{PWRGD_OUT}
Active Low Power Good
Output Low Voltage
I_PWRGD = 1mA, V_IN = –54V, ⎯P⎯W⎯R⎯G⎯D
●
Referenced to V_IN
I_{PWRGD_LEAK} Active Low Power Good Leakage
V_IN = 0V, V_PWRGD = 57V
●
1
V
0.5
V
1
µA
V_{PWRGD_OUT}
Active High Power Good
Output Low Voltage
I_PWRGD = 0.5mA, V_IN = –52V, V_OUT = –4V,
●
PWRGD Referenced to V_OUT (Note 14)
0.35
V
V_{PWRGD_VCLAMP} Active High Power Good
Voltage-Limiting Clamp
I_PWRGD = 2mA, V_OUT = 0V,
With Respect to V_OUT (Note 3)
● 12.0 14.0 16.5
V
I_{PWRGD_LEAK} Active High Power Good Leakage
V_PWRGD = 11V, with Respect to V_OUT,
●
V_OUT = V_IN = –54V
1
µA
R_ON
On Resistance
I = 700mA, V_IN = –54V
Measured from V_IN to V_OUT (Note 11)
●
0.5
0.6
Ω
0.8
Ω
I_{OUT_LEAK}
V_OUT Leakage
V_IN = –57V, GND = SHDN = V_OUT = 0V
●
1
µA
I_{LIMIT_HIGH}
Input Current Limit During Normal
V_IN = –54V, V_OUT = –53V, I_{LIM_EN} Floating
● 700
750
800
mA
Operation
(Notes 15, 16)
I_{LIMIT_LOW}
Inrush Current Limit
V_IN = –54V, V_OUT = –53V (Notes 15, 16)
● 250
300
350
mA
I_{LIMIT_DISA}
Safeguard Current Limit when
I_{LIMIT_HIGH} Disabled
V_IN = –54V, V_OUT = –52.5V, I_{LIM_EN} Tied to V_IN
1.20 1.45 1.65
A
(Notes 15, 16, 17)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and
lifetime.
Note 2: All voltages are with respect to GND pin unless otherwise noted.
Note 3: Active high PWRGD pin internal clamp circuit self-regulates to 14V
with respect to V_OUT.
Note 4: The LTC4264 operates with a negative supply voltage in the range of
–1.5V to –57V. To avoid confusion, voltages in this data sheet are referred to
in terms of absolute magnitude.
Note 5: In IEEE 802.3af systems, the maximum voltage at the PD jack is
defined to be –57V. See Applications Information.
Note 6: The LTC4264 is designed to work with two polarity protection
diodes in series with the input. Parameter ranges specified in the Electrical
Characteristics are with respect to LTC4264 pins and are designed to meet
IEEE 802.3af specifications when the drop from the two diodes is included.
See Applications Information.
Note 7: Signature resistance is measured via the two-point ΔV/ΔI method
as defined by IEEE 802.3af. The LTC4264 signature resistance is offset
from 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af
specifications. The minimum probe voltages measured at the LTC4264 pins
are – 1.5V and – 2.5V. The maximum probe voltages are –9.1V and –10.1V.
Note 8: The LTC4264 includes hysteresis in the UVLO voltages to preclude
any start-up oscillation. Per IEEE 802.3af requirements, the LTC4264 will
power up from a voltage source with 20Ω series resistance on the first trial.
Note 9: I_{IN_CLASS} does not include classification current programmed at
Pin 3. Total supply current in classification mode will be I_{IN_CLASS} + I_CLASS
(see Note 10).
Note 10: I_CLASS is the measured current flowing through R_CLASS. ΔI_CLASS
accuracy is with respect to the ideal current defined as I_CLASS = 1.237/R_CLASS.
t_CLASSRDY is the time for I_CLASS to settle to within ±3.5% of ideal. The current
accuracy specification does not include variations in R_CLASS resistance. The
total classification current for a PD also includes the IC quiescent current
(I_{IN_CLASS}). See Applications Information.
Note 11: This parameter is assured by design and wafer level testing.
Note 12: To disable the 25k signature, tie SHDN to GND (±0.1V) or hold SHDN
pin high with respect to V_IN. See Applications Information.
Note13: I_{LIM_EN} pin is pulled high internally and for normal operation should
be left floating. To disable high level current limit, tie I_{LIM_EN} to V_IN. See
Applications Information.
Note 14: Active high power good is referenced to V_OUT and is valid for
GND-V_OUT ≥ 4V. Measured at –52V due to test hardware limitations.
Note 15: The LTC4264 includes a dual current limit. At turn-on, before C1 is
charged, the LTC4264 current level is set to I_{LIMIT_LOW}. After C1 is charged
and with I_{LIM_EN} floating, the LTC4264 switches to I_{LIMIT_HIGH}. With I_{LIM_EN}
pin tied low, the LTC4264 switches to I_{LIMIT_DISA}. The LTC4264 stays in
I_{LIMIT_HIGH} or I_{LIMIT_DISA} until the input voltage drops below the UVLO turn-
off threshold or a thermal overload occurs.
Note 16: The LTC4264 features thermal overload protection. In the event of
an overtemperature condition, the LTC4264 will turn off the power MOSFET,
disable the classification load current and present an invalid power good
signal. Once the LTC4264 cools below the overtemperature limit, the
LTC4264 current limit switches to I_{LIMIT_LOW} and normal operation resumes.
Thermal overload protection is intended to protect the device during
momentary fault conditions and continuous operation in thermal overload
should be avoided as it may impair device reliability.
Note 17: I_{LIMIT_DISA} is a safeguard current limit that is activated when the
normal input current limit (I_{LIMIT_HIGH}) is defeated using the I_{LIM_EN} pin.
Currents at or near I_{LIMIT_DISA} will cause significant package heating and may
require a reduced maximum ambient operating temperature in order to avoid
tripping the thermal overload protection. See Applications Information.
4264f
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