LTC1325 Datasheet, PDF (3/24 Pages) Linear Technology – Microprocessor-Controlled Battery Management System

LTC1325
ELECTRICAL CHARACTERISTICS V_DD = 12V ±5%, T_A = 25°C, unless otherwise noted.
SYMBOL PARAMETER
V_OL
Output Low Voltage
V_OH
Output High Voltage
I_OZ
Hi-Z Output Leakage
V_OHFET
DIS or PGATE Output High
V_OLFET
DIS or PGATE Output Low
t_dDO
Delay Time, CLK↓ to D_OUT Valid
t_dis
Delay Time, CS↑ to D_OUT Hi-Z
t_en
Delay Time, CLK↓ to D_OUT Enabled
t_hDO
Time D_OUT Remains Valid After CLK↓
t_rDOUT
D_OUT Rise Time
t_fDOUT
D_OUT Fall Time
f_CLK
Serial I/O Clock Frequency
t_rPGATE
PGATE Rise Time
t_fPGATE
PGATE Fall Time
f_OSC
Internal Oscillator Frequency
A/D Converter
Offset Error
Linearity Error
Full-Scale Error
On-Channel Leakage
Off-Channel Leakage
CONDITIONS
D_OUT, I_OUT = 1.6mA
D_OUT, I_OUT = – 1.6mA
V_CS = 5V
V_DD = 4.5V to 16V
V_DD = 4.5V to 16V
See Test Circuits
See Test Circuits
See Test Circuits
See Test Circuits
See Test Circuits
See Test Circuits
CLK Pin
C_LOAD = 1500pF
C_LOAD = 1500pF
Charge Mode, Fail-Safes Disabled
V_IN Channel (Note 3)
V_IN Channel (Notes 3, 4)
V_IN Channel (Note 3)
V_IN Channel ON Only (Notes 3, 5)
V_IN Channel OFF (Notes 3, 5)
MIN TYP MAX
q
0.4
q
2.4
q
±10
q V_DD – 0.05
q
0.05
q
650
q
510
q
400
q
30
q
250
q
100
q
25
500
q
150
q
150
90
111 130
q
±2
q
±0.5
q
±1
q
±10
q
±10
UNITS
V
V
µA
V
V
ns
ns
ns
ns
ns
ns
kHz
ns
ns
kHz
LSB
LSB
LSB
µA
µA
RECO E DED CHARACTERISTICS
SYMBOL
t_hDI
t_dsuCS
t_dsuDI
t_WHCLK
t_WLCLK
t_WHCS
t_WLCS
PARAMETER
Hold Time, D_IN After CLK↑
Setup Time, CS Before First CLK↑
Setup Time, D_IN Stable Before First CLK↑
CLK High Time
CLK Low Time
CS High Time Between Data Transfers
CS Low Time During Data Transfer
CONDITIONS
MSBF = 1
MSBF = 0
MIN TYP MAX
UNITS
150
ns
1
µs
400
ns
0.8
µs
1
µs
1
µs
43
CLK Cycles
52
CLK Cycles
The q denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to the GND pin.
Note 3: V_REG within specified min and max limits, CLK (Pin 5) = 500kHz,
unless otherwise stated. ADC clock is the serial CLK.
Note 4: Linearity error is specified between the actual end points of the
A/D transfer curve.
Note 5: Channel leakage is measured after channel selection.
Note 6: Gas gauge offset excludes A/D offset error.
Note 7: I = V_DAC(Duty Ratio)/R_SENSE, where V_DAC is the DAC output
voltage with control bits VR1 = VR0 = 1, duty ratio = 1 and R_SENSE is
determined by the user.
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