LT1016_15 Datasheet, PDF (3/20 Pages) Linear Technology – UltraFast Precision 10ns Comparator

LT1016
Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. V⁺ = 5V, V^– = 5V, V_OUT (Q) = 1.4V, V_LATCH = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
LT1016C/I
MIN
TYP
MAX
UNITS
V_OS
Input Offset Voltage
R_S ≤ 100Ω (Note 2)
1.0
±3
mV
●
3.5
mV
∆V_OS /∆T
I_OS
Input Offset Voltage Drift
Input Offset Current
(Note 2)
●
4
µV/°C
0.3
1.0
µA
●
0.3
1.3
µA
I_B
Input Bias Current
(Note 3)
5
10
µA
●
13
µA
Input Voltage Range
(Note 6)
Single 5V Supply
● –3.75
● 1.25
3.5
V
3.5
V
CMRR
Common Mode Rejection
–3.75V ≤ V_CM ≤ 3.5V
● 80
96
dB
PSRR
Supply Voltage Rejection
Positive Supply 4.6V ≤ V⁺ ≤ 5.4V
● 60
75
dB
LT1016C
Positive Supply 4.6V ≤ V⁺ ≤ 5.4V
● 54
75
dB
LT1016I
Negative Supply 2V ≤ V^– ≤ 7V
● 80
100
dB
A_V
Small-Signal Voltage Gain
1V ≤ V_OUT ≤ 2V
1400
3000
V/V
V_OH
Output High Voltage
V⁺ ≥ 4.6V
I_OUT =1mA
● 2.7
3.4
V
I_OUT = 10mA
● 2.4
3.0
V
V_OL
Output Low Voltage
I⁺
Positive Supply Current
I_SINK = 4mA
●
I_SINK = 10mA
●
0.3
0.5
V
0.4
V
25
35
mA
I^–
Negative Supply Current
●
3
5
mA
V_IH
LATCH Pin Hi Input Voltage
V_IL
LATCH Pin Lo Input Voltage
I_IL
LATCH Pin Current
V_LATCH = 0V
t_PD
Propagation Delay (Note 4)
∆V_IN = 100mV, OD = 5mV
● 2.0
V
●
0.8
V
●
500
µA
10
14
ns
●
16
ns
∆V_IN = 100mV, OD = 20mV
9
12
ns
●
15
ns
∆t_PD
Differential Propagation Delay
(Note 4) ∆V_IN = 100mV,
OD = 5mV
3
ns
Latch Setup Time
2
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Input offset voltage is defined as the average of the two voltages
measured by forcing first one output, then the other to 1.4V. Input offset
current is defined in the same way.
Note 3: Input bias current (I_B) is defined as the average of the two input
currents.
Note 4: t_PD and ∆t_PD cannot be measured in automatic handling equipment
with low values of overdrive. The LT1016 is sample tested with a 1V step
and 500mV overdrive. Correlation tests have shown that t_PD and ∆t_PD
limits shown can be guaranteed with this test if additional DC tests are
performed to guarantee that all internal bias conditions are correct. For low
overdrive conditions V_OS is added to overdrive. Differential propogation
delay is defined as: ∆t_PD = t_PDLH – t_PDHL
Note 5: Electrical specifications apply only up to 5.4V.
Note 6: Input voltage range is guaranteed in part by CMRR testing and
in part by design and characterization. See text for discussion of input
voltage range for supplies other than ±5V or 5V.
Note 7: This parameter is guaranteed to meet specified performance
through design and characterization. It has not been tested.
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