LTC4252B-2_15 Datasheet, PDF (29/36 Pages) Linear Technology – Negative Voltage Hot Swap Controllers

LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
APPLICATIONS INFORMATION
END OF INTIAL TIMING CYCLE
END OF INTIAL TIMING CYCLE
12 34 567 7a
8 9 10 11
TIMER
V_TMRH 230µA + 8 • I_DRN
V_TMRL
5.8µA
GATE
V_GS(th)
58µA
20 • (V_ACL + V_OS)
SS
20 • (V_CB + V_OS)
20 • V_OS
SENSE
58µA
V_IN – V_GATEH
V_ACL
V_CB
12 3 4 5 6
7
8 9 10 11
TIMER
V_TMRH 230µA + 8 • I_DRN
V_TMRL
5.8µA
GATE
V_GS(th)
SS
58µA
20 • (V_ACL + V_OS)
20 • V_OS
SENSE
58µA
V_IN – V_GATEH
20 • (V_CB + V_OS)
V_ACL
V_CB
DRAIN
V_DRNCL
V_DRNL
DRAIN
V_DRNCL
V_DRNL
PWRGD
PWRGD
4252B12 F18
(18a) Without External C_SS
(18b) With External C_SS
Figure 18. Soft-Start Timing (All Waveforms Are Referenced to V_EE)
current begins to decline below V_ACL(t). The current limit
loop shuts off and GATE releases at time point 8. At time
point 9, the SENSE voltage falls below V_CB and TIMER
deactivates.
Large values of C_SS can cause premature circuit breaker
time out as V_ACL(t) may exceed the V_CB potential during
the circuit breaker delay. The load capacitor is unable to
achieve full charge in one GATE start-up cycle. A more
serious side effect of large C_SS values is SOA duration
may be exceeded during soft-start into a low impedance
load. A soft-start voltage below V_CB will not activate the
circuit breaker TIMER.
Power Limit Circuit Breaker
Figure 19 shows the LTC4252C-1 in a power limit circuit
breaking application. The SENSE pin is modulated by the
board supply voltage, V_SUPPLY. The D1 Zener voltage, V_Z
is set to be the same as the low supply operating volt-
age, V_SUPPLY(MIN) = 43V. If the goal is to have the high
supply operating voltage, V_SUPPLY(MAX) = 71V giving the
same power at V_SUPPLY(MIN), then resistors R4 and R6 are
selected using the ratio:
R6 ₌
V_CB
R4 V_SUPPLY(MAX)
(16)
If R6 is 27Ω, R4 is 38.3k. The peak circuit breaker power
limit is:
( )²
POWER_MAX
=
V_SUPPLY(MIN) +V_SUPPLY(MAX)
4 • V_SUPPLY(MIN) • V_SUPPLY(MAX)
• POWER_SUPPLY(MIN)
(17)
=1.064 •POWER_SUPPLY(MIN)
when
V_SUPPLY = 0.5 • (V_SUPPLY(MIN) + V_SUPPLY(MAX)) = 57V.
The peak power at the fault current limit occurs at the supply
overvoltage threshold. The fault current limited power is:
POWER_FAULT =
( ) VSUPPLY
R_S
•


V_ACL
–
V_SUPPLY –V_Z
•
R6
R4


(18)
4252b12f
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