LTC2435 Datasheet, PDF (29/40 Pages) Linear Technology – 20-Bit No Latency ADCs with Differential Input and Differential Reference

LTC2435/LTC2435-1
APPLICATIO S I FOR ATIO
100
V_CC = 5V
90 V_REF+ = 5V
80
V_REF– = GND
V_IN+ = 3.75V
70 ^VIN– ^{= 1.25V}
F_O = GND
60 _{TA = 25°C}
50
40
C_IN = 1µF, 10µF
C_IN = 0.1µF
30
20
C_IN = 0.01µF
10
0
0
400 800 1200 1600 2000
R_SOURCE (Ω)
2435 F23
Figure 23. +FS Error vs R_SOURCE at REF⁺ and REF^– (Large C_REF)
0
–10
C_IN = 0.01µF
–20
–30
–40
–50
–60 ^VCC ^{= 5V}
C_IN = 1µF, 10µF
V_REF+ = 5V
–70 V_REF– = GND
–80
V_IN+ = 1.25V
V_IN– = 3.75V
–90 ^FO ^{= GND}
T_A = 25°C
–100
0
400 800 1200
C_IN = 0.1µF
1600 2000
R_SOURCE (Ω)
2435 F24
Figure 24. –FS Error vs R_SOURCE at REF⁺ and REF^– (Large C_REF)
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When F_O = LOW (internal oscillator and 60Hz notch), every
100Ω of source resistance driving REF⁺ or REF^– translates
into about 0.11ppm additional INL error. For the LTC2435,
when F_O = HIGH (internal oscillator and 50Hz notch), every
100Ω of source resistance driving REF⁺ or REF^– translates
into about 0.092ppm additional INL error; and for the
LTC2435-1 operating with simultaneous 50Hz/60Hz re-
jection, every 100Ω of source resistance leads to an
additional 0.10ppm of additional INL error. When F_O is
driven by an external oscillator with a frequency f_EOSC,
every 100Ω of source resistance driving REF⁺ or REF^–
translates into about 0.73 • 10^–6 • f_EOSCppm additional INL
error. Figure 25 shows the typical INL error due to the
source resistance driving the REF⁺ or REF^– pins when
large C_REF values are used. The effect of the source
resistance on the two reference pins is additive with
respect to this INL error. In general, matching of source
impedance for the REF⁺ and REF^– pins does not help the
gain or the INL error. The user is thus advised to minimize
the combined source impedance driving the REF⁺ and
REF^– pins rather than to try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
(50ppm/°C) are used for the external source impedance
seen by REF⁺ and REF^–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05µV typical and 0.5µV maxi-
mum full-scale error.
15 _{VINCM = 0.5 • (IN+ + IN –) = 2.5V}
12 V_CC = 5V
REF+ = 5V
9 _{REF– = GND}
6 ^{FO = GND}
C_REF = 10µF
3 T_A = 25°C
0
R_SOURCE = 1k
–3
–6
R_SOURCE = 5k
–9
–12
R_SOURCE = 10k
–15
–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5
V_INDIF/V_REFDIF (V)
2435 F25
Figure 25. INL
and Reference
vSsouDricffeerReenstiiastlaInncpeut(RV_So_Olt_Ua_Rg_Ce_E(aVt_INRE=FI+Na⁺_n–dIN^–)
REF^– for Large C_REF Values (C_REF ≥ 1µF)
24351fa
29