LTP5901-IPR_15 Datasheet, PDF (28/32 Pages) Linear Technology – SmartMesh IP Network Manager 2.4GHz 802.15.4e Wireless Embedded Manager

LTP5901-IPR/LTP5902-IPR
Operation
IP Manager Options
The IP manager is offered in three different dash code
options, the -IPRA, -IPRB and -IPRC. The -IPRA option
supports managing networks of 32 motes or less with a
packet throughput of 24 packets per second.The -IPRB
option supports managing networks of 100 motes or
less with a packet throughput of 36 packets per second.
The -IPRC option supports managing networks of 32
motes or less with a packet throughput of 36 packets
per second. The -IPRA option does not support the use
of external SRAM. The -IPRB and -IPRC options require
the use of external SRAM, as described in the LTP5901
and LTP5902 Integration Guide. -IPRC managers can be
upgraded to support managing networks of up to 100
motes by purchasing a software license key as described
in the SmartMesh IP Users Guide.
State Diagram
In order to provide capabilities and flexibility in addition
to ultra low power, Eterna operates in various states, as
shown in Figure 10 Eterna State Diagram and described
in this section. State transitions shown in red are not
recommended.
Start-Up
Start-up occurs as a result of either crossing the power-on
reset threshold or asserting RESETn. After the completion
of power-on reset or the falling edge of an internally
synchronized RESETn, Eterna loads its fuse table which,
as described in the previous section, includes setting
I/O direction. In this state, Eterna checks the state of
the FLASH_P_ENn and RESETn and enters the serial
flash emulation mode if both signals are asserted. If the
FLASH_P_ENn pin is not asserted but RESETn is asserted,
Eterna automatically reduces its energy consumption to
a minimum until RESETn is released. Once RESETn is
de-asserted, Eterna goes through a boot sequence, and
then enters the active state.
Serial Flash Emulation
When both RESETn and FLASH_P_ENn are asserted,
Eterna disables normal operation and enters a mode to
emulate the operation of a serial flash. In this mode, its
flash can be programmed.
Operation
Once Eterna has completed start-up, Eterna transitions to
the operational group of states (active/CPU active, active/
CPU inactive, and Doze). There, Eterna cycles between the
various states, automatically selecting the lowest pos-
sible power state while fulfilling the demands of network
operation.
Active State
In the active state, Eterna’s relaxation oscillator is running
and peripherals are enabled as needed. The ARM Cortex-
M3 cycles between CPU-active and CPU-inactive (referred
to in the ARM Cortex-M3 literature as sleep now mode).
Eterna’s extensive use of DMA and intelligent peripherals
that independently move Eterna between active state and
doze state minimizes the time the CPU is active, signifi-
cantly reducing Eterna’s energy consumption.
Doze State
The doze state consumes orders of magnitude less cur-
rent than the active state and is entered when all of the
peripherals and the CPU are inactive. In the Doze state
Eterna’s full state is retained, timing is maintained, and
Eterna is configured to detect, wake, and rapidly respond
to activity on I/Os (such as UART signals and the TIMEn
pin). In the doze state the 32.768kHz oscillator and as-
sociated timers are active.
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For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR
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