LTC1708-PG Datasheet, PDF (27/32 Pages) Linear Technology – Dual Adjustable 5-Bit VID High Efficiency, 2-Phase Current Mode Synchronous Buck Regulator Controller

LTC1708-PG
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1708. These items are also illustrated graphically in
the layout diagram of Figure 10. The Figure 11 illustrates
the current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at C_IN? Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined LTC1708 signal ground pin and the ground
return of C_INTVCC must return to the combined C_OUT (–)
terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the C_IN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible to the
(–) terminals of the input capacitor by placing the
INTV_CC
INTV_CC
1
RUN/SS1
36
PGOOD
2 _SENSE1+
35
TG1
3 _SENSE1–
34
SW1
4
EAIN1
33
BOOST1
5
FREQSET
6
STBYMD
32
V_IN
31
BG1
7
FCB
30
EXTV_CC
8
I_TH1
29
INTV_CC
9
SGND
28
PGND
10
LTC1708-PG
27
3.3V_OUT
BG2
11
I_TH2
26
BOOST2
12
EAIN2
25
SW2
13 _SENSE2–
24
TG2
14 _SENSE2+
23
RUN/SS2
15
ATTNOUT
16
ATTNIN
22
VIDV_CC
21
VID4
17
VID0
20
VID3
18
VID1
19
VID2
VID CONTROL
INPUTS
POWER GOOD
INTV_CC
V_OUT1
V_IN
V_OUT2
1708 F10
Figure 10. LTC1708 Recommended Printed Circuit Layout Diagram
27