LTC2480_15 Datasheet, PDF(25/42 Page) Linear Technology – 16-Bit ADC with Easy Drive Input Current Cancellation

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LTC2480_15 Datasheet, PDF (25/42 Pages) Linear Technology – 16-Bit ADC with Easy Drive Input Current Cancellation

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LTC2480

APPLICATIONS INFORMATION

CS remains LOW during the data output state. However,

the data output state may be aborted by pulling CS HIGH

anytime between the first and 24th rising edge of SCK (see

Figure 9). On the rising edge of CS, the device aborts the

data output state and immediately initiates a new conver-

sion. If the device has not finished loading the last input

bit SPD of SDI by the time CS is pulled HIGH, the SDI

information is discarded and the previous configuration

is still kept. This is useful for systems not requiring all 24

bits of output data, aborting an invalid conversion cycle,

or synchronizing the start of a conversion. If CS is pulled

HIGH while the converter is driving SCK LOW, the internal

pull-up is not available to restore SCK to a logic HIGH state.

This will cause the device to exit the internal serial clock

mode on the next falling edge of CS. This can be avoided

by adding an external 10k pull-up resistor to the SCK pin

or by never pulling CS HIGH when SCK is LOW.

Whenever SCK is LOW, the LTC2480âs internal pull-up at

pin SCK is disabled. Normally, SCK is not externally driven

if the device is in the internal SCK timing mode. However,

certain applications may require an external driver on SCK.

If this driver goes Hi-Z after outputting a LOW signal, the

LTC2480âs internal pull-up remains disabled. Hence, SCK

remains LOW. On the next falling edge of CS, the device is

switched to the external SCK timing mode. By adding an

external 10k pull-up resistor to SCK, this pin goes HIGH

once the external driver goes Hi-Z. On the next CS falling

edge, the device will remain in the internal SCK timing

mode.

A similar situation may occur during the sleep state when

CS is pulsed HIGH-LOW-HIGH in order to test the conver-

sion status. If the device is in the sleep state (EOC = 0),

SCK will go LOW. Once CS goes HIGH (within the time

period defined above as tEOCtest), the internal pull-up is

activated. For a heavy capacitive load on the SCK pin, the

internal pull-up may not be adequate to return SCK to a

HIGH level before CS goes low again. This is not a concern

under normal conditions where CS remains LOW after

detecting EOC = 0. This situation is easily overcome by

adding an external 10k pull-up resistor to the SCK pin.

>tEOCtest

TEST EOC

(OPTIONAL)

<tEOCtest

2.7V TO 5.5V

1ÂµF

2 VCC

fO 10

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG

INPUT

LTC2480

3 VREF

SDI 1

SCK 9

4 IN+

5 INâ

SDO 7

CS 6

GND

INT/EXT CLOCK

VCC

10k

4-WIRE

SPI INTERFACE

SDO

Hi-Z

BIT 0

EOC

TEST EOC

Hi-Z

BIT 23 BIT 22

EOC

Hi-Z

BIT 21

SIG

BIT 20

MSB

BIT 19

BIT 18

BIT 17 BIT 16

SCK

(INTERNAL)

SDI*

DONâT CARE

SLEEP

DATA

OUTPUT

CONVERSION

SLEEP

GS2

GS1

GS0

DATA OUTPUT

SPD

Figure 9. Internal Serial Clock, Reduce Data Output Length

For more information www.linear.com/LTC2480

BIT 8

TEST EOC

Hi-Z

DONâT CARE

CONVERSION

2480 F09

2480fe

▷