LTC2412 Datasheet, PDF (25/36 Pages) Linear Technology – 2-Channel Differential Input 24-Bit No Latency DS ADC

LTC2412
APPLICATIO S I FOR ATIO
of input multiplexers, wires, connectors or sensors, the
LTC2412 can maintain its exceptional accuracy while
operating with relative large values of source resistance as
shown in Figures 13 and 14. These measured results may
be slightly different from the first order approximation
suggested earlier because they include the effect of the
actual second order input network together with the non-
linear settling process of the input amplifiers. For small C_IN
values, the settling on IN⁺ and IN^– occurs almost indepen-
dently and there is little benefit in trying to match the
source impedance for the two pins.
Larger values of input capacitors (C_IN > 0.01µF) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When F_O = LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 1.8MΩ which will
generate a gain error of approximately 0.28ppm at full-
scale for each ohm of source resistance driving IN⁺ or IN.
When F_O = HIGH (internal oscillator and 50Hz notch), the
typical differential input resistance is 2.16MΩ which will
generate a gain error of approximately 0.23ppm at full-
scale for each ohm of source resistance driving IN⁺ or IN.
When F_O is driven by an external oscillator with a fre-
quency f_EOSC (external conversion clock operation), the
typical differential input resistance is 0.28 • 10¹²/f_EOSCΩ
and each ohm of source resistance driving IN⁺ or IN^– will
result in 1.78 • 10^–6 • f_EOSCppm gain error at full-scale. The
effect of the source resistance on the two input pins is
additive with respect to this gain error. The typical +FS and
–FS errors as a function of the sum of the source resis-
tance seen by IN⁺ and IN^– for large values of C_IN are shown
in Figures 15 and 16.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN⁺ and IN^– and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the con-
verter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large C_IN capacitor
300
V_CC
REF
= 5V
+ _{= 5V}
240
REF ^– = GND
IN⁺ = 3.75V
IN^– = 1.25V
F_O = GND
180 _{TA = 25°C}
120
60
C_IN = 1µF, 10µF
C_IN = 0.1µF
C_IN = 0.01µF
0
0 100 200 300 400 500 600 700 800 900 1000
R_SOURCE (Ω)
2412 F15
Figure 15. +FS Error vs R_SOURCE at IN⁺ or IN^– (Large C_IN)
0
C_IN = 0.01µF
–60
–120
C_IN = 0.1µF
–180
–240
RV^CE^CF^+==5V5V
REF ^– = GND
IN⁺ = 1.25V
IN^– = 3.75V
F_O = GND
T_A = 25°C
–300
C_IN = 1µF, 10µF
0 100 200 300 400 500 600 700 800 900 1000
R_SOURCE (Ω)
2412 F16
Figure 16. –FS Error vs R_SOURCE at IN⁺ or IN^– (Large C_IN)
values, it is advisable to carefully match the source imped-
ance seen by the IN⁺ and IN^– pins. When F_O = LOW
(internal oscillator and 60Hz notch), every 1Ω mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.28ppm. When F_O = HIGH (internal oscillator and 50Hz
notch), every 1Ω mismatch in source impedance trans-
forms a full-scale common mode input signal into a differ-
ential mode input signal of 0.23ppm. When F_O is driven by
an external oscillator with a frequency f_EOSC, every 1Ω
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 1.78 • 10^–6 • f_EOSCppm. Figure 17 shows the
typical offset error due to input common mode voltage for
2412f
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