LTC2230_1 Datasheet, PDF (25/32 Pages) Linear Technology – 10-Bit,170Msps/135Msps ADCs

LTC2230/LTC2231
APPLICATIO S I FOR ATIO
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV_DD, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply then OV_DD should be tied to that same 1.8V supply.
In the CMOS output mode, OV_DD can be powered with any
voltage up to 3.6V. OGND can be powered with any voltage
from GND up to 1V and must be less than OV_DD. The logic
outputs will swing between OGND and OV_DD.
In the LVDS output mode, OV_DD should be connected to a
3.3V supply and OGND should be connected to GND.
Output Enable
The outputs may be disabled with the output enable pin, OE.
In CMOS or LVDS output modes OE high disables all data
outputs including OF and CLKOUT. The data access and bus
relinquish times are too slow to allow the outputs to be
enabled and disabled during full speed operation. The output
Hi-Z state is intended for use during long periods of inac-
tivity.
The Hi-Z state is not a truly open circuit; the output pins that
make an LVDS output pair have a 20k resistance between
them. Therefore in the CMOS output mode, adjacent data
bits will have 20k resistance in between them, even in the
Hi-Z state.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V_DD and OE to V_DD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to V_DD and OE
to GND results in nap mode, which typically dissipates
35mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap mode all digital outputs are disabled and enter the
Hi-Z state.
GROUNDING AND BYPASSING
The LTC2230/LTC2231 requires a printed circuit board with
a clean unbroken ground plane. A multilayer board with an
internal ground plane is recommended. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particu-
lar, care should be taken not to run any digital track along-
side an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the V_DD, OV_DD, V_CM, REFHA, REFHB, REFLA and REFLB pins
as shown in the block diagram on the front page of this data
sheet. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capaci-
tors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recommended. The 2.2μF capacitor between REFHA and
REFLA can be somewhat further away. The traces connect-
ing the pins and bypass capacitors must be kept short and
should be made as wide as possible.
The LTC2230/LTC2231 differential inputs should run par-
allel and close to each other. The input traces should be as
short as possible to minimize capacitance and to minimize
noise pickup.
HEAT TRANSFER
Most of the heat generated by the LTC2230/LTC2231 is
transferred from the die through the bottom-side exposed
pad and package leads onto the printed circuit board. For
good electrical and thermal performance, the exposed pad
should be soldered to a large grounded pad on the PC board.
It is critical that all ground pins are connected to a ground
plane of sufficient area.
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