LTC2874_15 Datasheet, PDF (24/44 Pages) Linear Technology – Quad IO-Link Master Hot Swap Controller and PHY

LTC2874
Applications Information
Power Considerations
The LTC2874 has two power supply pins: a logic supply
pin (V_L) and the primary supply (V_DD). The V_L supply
powers the control logic, serial interface and SPI registers,
and allows the LTC2874 to interface with any logic signal
from 2.9V to 5.5V. Bypass V_L to GND with at least a 0.1µF
ceramic capacitor. There is no power supply sequencing
requirement.
Bypass capacitance between V_DD and GND is important
for reliable operation. If a short circuit occurs at one of
the L+ output ports, it can take more than 20µs for the
LTC2874 to begin regulating the current. During this time
the current is limited only by minimal impedance, so a high
current spike can cause a voltage transient on the V_DD
supply with the possibility that the LTC2874 resets due to
a UVLO fault. Decouple V_DD to ground with at least 100µF
bulk capacitance and a 1µF, 100V X7R ceramic capacitor
placed near the V_DD pin to minimize spurious resets.
Supply Monitors
The LTC2874 monitors various conditions on its two input
power supplies, and alerts the host microcontroller when
supply levels move outside of their operating range. Event
bits record when the logic supply V_L has moved below its
UVLO threshold or when the main supply V_DD has moved
below its UVLO threshold, below its mode-dependent UV
level, or above its programmable OV level (see Figure 23).
V_DD
18V
+
32V
34V
–
36V
OV_TH[1:0]
–
7V
+
17.5V
24VMODE
–
6V ⁺
V_L ^–
2V ⁺
POR
0V_VDD
10µs
EVENT
STATUS
UV_VDD
10µs
EVENT
UVLO_VDD
10µs
EVENT
STATUS
UVLO_VL
EVENT
2874 F23
To provide immunity against supply voltage spikes, the
V_DD event bits have a 10µs filter time. Status bits are live
(no-delay) indicators.
Operating Above 30V
When operating above 30V, the V_DD threshold at which
overvoltage circuits disable the CQ and L+ pins must be
set higher than the default value (32V). Choose a value of
34V or 36V using the OV_TH[1:0] register bits.
Auto-Retry or Latchoff Fault Response
When a line output is shorted or the ∆V_CB(TH) threshold is
otherwise exceeded, a timed circuit breaker disables the
L+ power supply output or CQ driver before overheating
can damage the MOSFET (L+) or master (CQ). Register
bits RETRY_L+ and RETRY_CQ allow independent fault
behavior for L+ and CQ pins. Set these bits high for auto-
retry behavior and low for latchoff. Default behavior is
auto-retry.
When configured for auto-retry behavior, the LTC2874
periodically re-enables the pin to check if the fault
condition is still present. See Erratum #1. The RE-
TRYTC[2:0] register bits adjust the retry timer delay
from 0.12s to 15.7s to allow for cooling. Choose retry
(RETRYTC) and overcurrent timer (LPTC) settings in tandem
to keep the duty cycle of an L+ fault condition sufficiently
low to allow for cooling of the external MOSFET. In the
case of a CQ fault condition, even the fastest RETRYTC
setting limits the duty cycle to <1% to allow for cooling
of one or more drivers.
When configured for latchoff behavior, the LTC2874
disables the respective L+ or CQ pin until the overcur-
rent event bit is cleared. In this case, clearing the event
register initiates a manual retry. The host is responsible
for limiting the duty cycle of the fault condition to avoid
overheating the L+ MOSFET or CQ driver. For example,
when using the highest available LPTC setting, a manual
retry interval of 1s limits the L+ MOSFET duty cycle to
20%. In SIO mode, a manual retry interval of 5ms limits
the CQ driver duty cycle to 10%.
Figure 23. Supply UVLO, UV, and OV Monitors
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