LTC2413 Datasheet, PDF (24/44 Pages) Linear Technology – 24-Bit No Latency ADC, with Simultaneous 50Hz/60Hz Rejection

LTC2413
APPLICATIO S I FOR ATIO
velocity is approximately 183ps/inch for internal traces
and 170ps/inch for surface traces. Thus, a driver gener-
ating a control signal with a minimum transition time of
1ns must be connected to the converter pin through a
trace shorter than 2.5 inches. This problem becomes
particularly difficult when shared control lines are used
and multiple reflections may occur. The solution is to
carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2413 pin will eliminate
this problem but will increase the driver power dissipation.
A series resistor between 27Ω and 56Ω placed near the
driver or near the LTC2413 pin will also eliminate this
problem without additional power dissipation. The actual
resistor value depends upon the trace impedance and
connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
Particular attention must be given to the connection of the
F_O signal when the LTC2413 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals may result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals may result in a DC offset error. Such
perturbations may occur due to asymmetric capacitive
coupling between the F_O signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the F_O signal trace and the input/reference sig-
nals. When the F_O signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the F_O connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the F_O signal as well as the loop area for
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2413 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these ca-
pacitors are switching between these four pins transfering
small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 16.
For a simple approximation, the source impedance R_S
driving an analog input pin (IN⁺, IN^–, REF⁺ or REF^–) can be
considered to form, together with R_SW and C_EQ (see
Figure␣ 16), a first order passive network with a time
constant τ = (R_S + R_SW) • C_EQ. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator (F_O = LOW), the
LTC2413’s front-end switched-capacitor network is clocked
at 69900Hz corresponding to a 14.3µs sampling period.
Thus, for settling errors of less than 1ppm, the driving
source impedance should be chosen such that
τ␣ ≤␣ 14.3µs/14 = 1.02µs. When an external oscillator of
frequency f_EOSC is used, the sampling period is 2/f_EOSC
and, for a settling error of less than 1ppm, τ ≤ 0.14/f_EOSC.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 16 shows the
mathematical expressions for the average bias currents
flowing through the IN⁺ and IN^– pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
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