LTC1876_15 Datasheet, PDF (24/36 Pages) Linear Technology – High Efficiency, 2-Phase, Dual Synchronous Step-Down Switching Controller and Step-Up Regulator

LTC1876
APPLICATIO S I FOR ATIO
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can be easily added to
the LTC1876 by loading the I_TH pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage of the error amplifier, or 1.2V
(see Figure 8).
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application. A
complete explanation is included in Design Solutions 10.
(See: www.linear-tech.com)
INTV_CC
R_T2
R_T1
I_TH
R_C
LTC1876
C_C
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Figure 8. Active Voltage Positioning Applied to the LTC1876
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1876 circuits: 1) LTC1876 V_IN current (in-
cluding loading on the 3.3V internal regulator), 2) INTV_CC
regulator current, 3) I²R losses, 4) topside MOSFET
transition losses.
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1. The V_IN current has two components: the first is the DC
supply current given in the Electrical Characteristics table,
which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output. V_IN current typically results in a small (<0.1%)
loss.
2. INTV_CC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV_CC to
ground. The resulting dQ/dt is a current out of INTV_CC that
is typically much larger than the control circuit current. In
continuous mode, I_GATECHG =f(Q_T+Q_B), where Q_T and Q_B
are the gate charges of the topside and bottom side
MOSFETs.
Supplying INTV_CC power through the EXTV_CC switch input
from an output-derived source will scale the V_IN current
required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV_CC current results in approxi-
mately 3mA of V_IN current. This reduces the mid-current
loss from 10% or more (if the driver was powered directly
from V_IN) to only a few percent.
3. I²R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R_SENSE,
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R_DS(ON), then the resistance of one
MOSFET can simply be summed with the resistances of L,
R_SENSE and ESR to obtain I²R losses. For example, if each
R_DS(ON) = 30mΩ, R_L = 50mΩ, R_SENSE = 10mΩ and R_ESR
= 40mΩ (sum of both input and output capacitance
losses), then the total resistance is 130mΩ. This results in
losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Efficiency varies as the inverse
square of V_OUT for the same external components and
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
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