LT1103 Datasheet, PDF (24/32 Pages) Linear Technology – Offline Switching Regulator

LT1103/LT1105
APPLICATIONS INFORMATION
compensation can be set to cancel the effects of these
parasitic voltage drops. The feature can be ignored by
eliminating the series resistor and lowering the equivalent
divider impedance to swamp out the effects of the input
bias current.
Frequency Compensation
In order to prevent a regulator loop using the LT1103/
LT1105 from oscillating, frequency compensation is
required. Although the architecture of the LT1103/LT1105
is simple enough to lend itself to a mathematical approach
to frequency compensation, the added complication of
input/or output filters, unknown capacitor ESR, and gross
operating point changes with input voltage and load current
variations all suggest a more practical empirical approach.
Many hours spent on breadboards have shown that the
simplest way to optimize the frequency compensation of
the LT1103/LT1105 is to use transient response techniques
and an “RC” box to quickly iterate toward the final
compensation network. Additional information on this
technique of frequency compensation can be found in
Linear Technology’s Application Note 19.
In general, frequency compensation is accomplished with
an RC series network on the V_C pin. The error amplifier has
a g_m (voltage “in” to current “out”) of ≈ 12000 µmhos.
Voltage gain is determined by multiplying g_m times the
total equivalent error amplifier output loading, consisting
of the error amplifier output impedance in parallel with the
series RC external frequency compensation network. At
DC, the external RC can be ignored. The output impedance
of the error amplifier is typically 100kΩ resulting in a
voltage gain of ≈ 1200V/V. At frequencies just above DC,
the voltage gain is determined by the external
compensation, R_C and C_C. The gain at mid frequencies is
given by:
A_V
=
2π
g_m
• f • C_C
The gain at high frequencies is given by:
A_V = g_m • R_C
Phase shift from the FB pin to the V_C pin is 90° at mid
frequencies where the external C_C is controlling gain, then
drops back to 0° (actually 180° since FB is an inverting
input) when the reactance of C_C is small compared to R_C.
Thus, this RC series network forms a pole-zero pair. The
pole is set by the high impedance output of the error
amplifier and the value of C_C on the V_C pin. The zero is
formed by the value of C_C and the value of R_C in series with
C_C on the V_C pin. The RC series network will have capacitor
values in the range of 0.1µF to 1.0µF and series resistor
values in the range of 100Ω to 1000Ω.
It is noted that the RC network on the V_C pin forms the main
compensation network for the regulator loop. However, if
the load regulation compensation feature is used as ex-
plained in the section on fully-isolated flyback mode,
additional frequency compensation components are re-
quired. The load regulation compensation feature involves
the use of local positive feedback from the V_C pin to the FB
pin. Thus, it is possible to add enough load regulation
compensation to make the loop oscillate. In order to
prevent oscillation, it is necessary to roll off this local
positive feedback at high frequencies. This is accom-
plished by placing a capacitor in parallel with the compen-
sation resistor which is in series with the FB pin. A value
for this capacitor in the range of 0.01µF to 0.1µF is
recommended. The time constant associated with this RC
combination will be longer than that associated with the
loop bandwidth. Thus, transient response will be affected
in that settling time will be increased. However, this is
typically not as important as controlling the absolute
under or overshoot amplitude of the system in response to
load current changes which could cause deleterious sys-
tem operation.
Switching Regulator Topologies
Two basic switching regulator topologies are pertinent to
the LT1103/LT1105, the flyback and forward converter.
The flyback converter employs a transformer to convert
one voltage to either a higher or lower output voltage. V_OUT
in continuous mode is defined as:
V_OUT
=
V_IN
•N•
DC
(1– DC)
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