LTM9002_15 Datasheet, PDF (23/28 Pages) Linear Technology – 14-Bit Dual-Channel IF/ Baseband Receiver Subsystem

LTM9002
APPLICATIONS INFORMATION
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this time delay exceeds 1ns,
the performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
Figure 10 and Figure 11 show alternatives for converting
a differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
to phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz will
degrade the SNR compared to the transformer solution.
The nature of the received signals also has a large bear-
ing on how much SNR degradation will be experienced.
For high crest factor signals such as WCDMA or OFDM,
where the nominal power level must be at least 6dB to
8dB below full-scale, the use of these translators will have
a lesser impact.
4.7μF
CLEAN
FERRITE ^SUPPLY
BEAD
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed
to ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The
use of a capacitor at the input may result in peaking, and
depending on transmission line length may require a 10Ω
to 20Ω series resistor to act as both a lowpass filter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTM9002-AA is
125Msps and the LTM9002-LA is 65Msps. The lower
limit of the sample rate is determined by the droop of the
sample-and-hold circuits. The pipelined architecture of
this ADC relies on storing analog signals on small valued
capacitors. Junction leakage will discharge the capaci-
tors. The specified minimum operating frequency for the
LTM9002 is 1Msps.
100Ω
0.1μF
CLK LTM9002
9002 F10
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 10. CLK Driver Using an LVDS or PECL to CMOS Converter
DIFFERENTIAL
CLOCK
INPUT
ETC1-1T
CLK LTM9002
5pF TO
30pF
0.1μF
FERRITE
BEAD
9002 F11
V_CM
Figure 11. LVDS or PECL CLK Driver Using a Transformer
9002f
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