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LTC2301 Datasheet, PDF (23/24 Pages) Linear Technology – 1-/2-Channel, 12-Bit ADCs with I2C Compatible Interface
LTC2301/LTC2305
PACKAGE DESCRIPTION
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)
0.70 ±0.05
4.00 ±0.10
(2 SIDES)
R = 0.05
TYP
R = 0.115
7
TYP
0.40 ± 0.10
12
3.60 ±0.05
2.20 ±0.05
3.30 ±0.05
1.70 ± 0.05
PIN 1
TOP MARK
PACKAGE (NOTE 6)
OUTLINE
3.00 ±0.10
(2 SIDES)
3.30 ±0.10
1.70 ± 0.10
0.25 ± 0.05
0.50 BSC
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.200 REF
0.75 ±0.05
0.00 – 0.05
6
0.25 ± 0.05
2.50 REF
1
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
(UE12/DE12) DFN 0806 REV D
MS Package
12-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1668 Rev Ø)
0.889 p 0.127
(.035 p .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.42 p 0.038
(.0165 p .0015)
TYP
0.65
(.0256)
BSC
RECOMMENDED SOLDER PAD LAYOUT
4.039 p 0.102
(.159 p .004)
(NOTE 3)
12 11 10 9 8 7
0.406 p 0.076
(.016 p .003)
REF
0.254
(.010)
GAUGE PLANE
0.18
(.007)
DETAIL “A”
0o – 6o TYP
4.90 p 0.152
(.193 p .006)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.53 p 0.152
(.021 p .006)
DETAIL “A”
SEATING
PLANE
1.10
(.043)
MAX
1 23 456
0.86
(.034)
REF
0.22 – 0.38
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
(.009 – .015)
TYP
0.650
(.0256)
BSC
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.1016 p 0.0508
(.004 p .002)
MSOP (MS12) 1107 REV Ø
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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