LTC2241-12_15 Datasheet, PDF (23/30 Pages) Linear Technology – 12-Bit, 210Msps ADC

LTC2241-12
Applications Information
The lowest phase noise oscillators have single-ended si-
nusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
the filter and the ADC. If the circuit is sensitive to close-
in phase noise, the power supply for oscillators and any
buffers must be very stable, or propagation delay variation
with supply will translate into phase noise. Even though
these clock sources may be regarded as digital devices,
do not operate them on a digital supply. If your clock is
also used to drive digital devices such as an FPGA, you
should locate the oscillator, and any clock fan-out devices
close to the ADC, and give the routing to the ADC prece-
dence. The clock signals to the FPGA should have series
termination at the driver to prevent high frequency noise
from the FPGA disturbing the substrate of the clock fan-out
device. If you use an FPGA as a programmable divider, you
must re-time the signal using the original oscillator, and
the re-timing flip-flop as well as the oscillator should be
close to the ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated in
the waveguides that exist between the layers of multilayer
PCBs. The differential pairs must be close together and
distanced from other signals. The differential pair should
be guarded on both sides with copper distanced at least
3x the distance between the traces, and grounded with
vias no more than 1/4 inch apart.
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