LTC2207-14_15 Datasheet, PDF (23/32 Pages) Linear Technology – 14-Bit, 105Msps/80Msps ADCs

LTC2207-14/LTC2206-14
APPLICATIONS INFORMATION
DIGITAL OUTPUTS
Digital Output Buffers
Figure 11 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV_DD and OGND, isolated
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
eliminates the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2207-14/LTC2206-14 should drive
a minimum capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as a
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF. A resistor in
series with the output may be used but is not required since
the output buffer has a series resistor of 33Ω on chip.
Lower OV_DD voltages will also help reduce interference
from the digital outputs.
Table 1. MODE Pin Function
MODE OUTPUT FORMAT
0(GND)
Offset Binary
1/3V_DD
2/3V_DD
V_DD
Offset Binary
2’s Complement
2’s Complement
CLOCK DUTY CYCLE STABILIZER
Off
On
On
Off
Overflow Bit
An overflow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overflow or underflow.
Output Clock
The ADC has a delayed version of the encode input available
as a digital output. Both a noninverted version, CLKOUT+
and an inverted version CLKOUT– are provided. The
CLKOUT+/CLKOUT– can be used to synchronize the
LTC2207-14/LTC2206-14
CLKOUT
CLKOUT⁺
Data Format
OF
The LTC2207-14/LTC2206-14 parallel digital output can
be selected for offset binary or 2’s complement format.
The format is selected with the MODE pin. This pin has a
D13
four level logic input, centered at 0, 1/3V_DD, 2/3V_DD and
V_DD. An external resistor divider can be used to set the
D12
1/3V_DD and 2/3V_DD logic levels. Table 1 shows the logic
states for the MODE pin.
V_DD
DATA
FROM
LATCH
PREDRIVER
LOGIC
LTC2207-14/LTC2206-14
OV_{DD 0.5V}
V_DD
TO 3.6V
0.1μF
OV_DD
33Ω
TYPICAL
DATA
OUTPUT
OGND
D2
D1
RAND = HIGH,
SCRAMBLE
ENABLED
RAND
D0
OF
D13/D0
D12/D0
•
•
•
D2/D0
D1/D0
D0
2207614 F11
Figure 11. Equivalent Circuit for a Digital Output Buffer
2207614 F12
Figure 12. Functional Equivalent of Digital Output Randomizer
220714614fc
23