LTC1853_15 Datasheet, PDF (23/24 Pages) Linear Technology – 8-Channel, 10-Bit/12-Bit, 400ksps, Low Power, Sampling ADCs

LTC1852/LTC1853
TYPICAL APPLICATIONS
LTC1853 Hardwired for 4-Channel Differential Scan with Bipolar ±1.024V Operation
5V
14
V_DD
15
V_DD
10μF
0.1μF
LTC1853
+
–
+
INPUT
–
CONFIGURATION:
4 DIFFERENTIAL
+
CHANNELS: ±1.024V
–
+
–
1 CH0
2 CH1
3 CH2
4 CH3
5 CH4
6 CH5
7 CH6
8 CH7
9 COM
8-CHANNEL
MULTIPLEXER
INTERNAL
CLOCK
2.5V
1μF
10 REFOUT _2.5V
REFERENCE
+ ^12-BIT
–
SAMPLING
ADC
11 REFIN
REF AMP
4.096V
0.1μF
10μF
12 REFCOMP
1.6384X
GND
13
GND
16
M1 48
CONTROL LOGIC
AND
PROGRAMMABLE
SEQUENCER
M0 36
SHDN 47
CS 46
CONVST 45
RD 44
WR 43
DIFF 42
A2 41
A1 40
A0 39
UNI/BIP 38
PGA 37
OV_DD 35
BUSY 33
DIFF_OUT/S6 17
A2_OUT/S5 18
A1_OUT/S4 19
A0_OUT/S3 20
D11/S2 21
DATA
LATCHES
OUTPUT
DRIVERS
D10/S1 22
D9/S0 23
D8 24
D7 25
D6 26
D5 27
D4 28
D3 29
D2 30
D1 31
D0 32
OGND 34
18523 TA02
5V
5V
CONVERT
CLOCK
5V
5V
3V TO 5V
10μF
0.1μF
PACKAGE DESCRIPTION
48
FW Package
48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651 Rev A)
25
0.95 ±0.10
12.40 – 12.60*
(.488 – .496)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
8.4 ±0.10
6.2 ±0.10
7.9 – 8.3
(.311 – .327)
1
0.32 ±0.05
24
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
6.0 – 6.2**
(.236 – .244)
0.25
REF
0° – 8°
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2.
DIMENSIONS
ARE
IN
MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
0.09 – 0.20
(.0035 – .008)
0.45 – 0.75
(.018 – .029)
-C-
0.50
(.0197)
BSC
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS _{DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE}
0.17 – 0.27
(.0067 – .0106)
TYP
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
-T-
0.10 C
FW48 TSSOP REV A 1005
18523fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
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