LT1766 Datasheet, PDF (23/28 Pages) Linear Technology – Step-Down Switching Regulator

LT1766/LT1766-5
APPLICATIO S I FOR ATIO
(^R4)(^CSS )(^VOUT )
RiseTime =
V_BE
Using the values shown in Figure 10,
( )( ) ^{47 •103 15 •10–9 (5)}
Rise Time =
= 5ms
0.7
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can be
used for sequencing multiple regulator outputs.
D2
1N4148W
INPUT
40V
BOOST BIAS
C2
0.33µF
C3
V_IN
SW
2.2µF
50V
LT1766
D1
CER
SHDN
FB
SYNC GND V_C
R_C
2.2k
C_C
0.022µF
C_F
220pF ^Q1
L1
47µH
C1 ⁺
100µF
R3
C_SS
15nF
2k
R4
47k
OUTPUT
5V
1A
R1
15.4k
R2
4.99k
1766 F13
At switch off, energy is transferred by magnetic coupling
into L1B, powering the – 5V rail. C4 pulls L1B positive
during switch on time, causing current to flow, and energy
to build in L1B and C4. At switch off, the energy stored in
both L1B and C4 supply the –5V rail. This reduces the
current in L1A and changes L1B current waveform from
square to triangular. For details on this circuit, including
maximum output currents, see Design Note 100.
C2
0.33µF
V_IN
7.5V
TO 60V
C3
2.2µF
100V
CER
GND
BOOST
V_IN
SW
LT1766
SHDN
SYNC
FB
GND
V_C
R_C
2.2k
C_C
0.022µF
C_F
220pF
C4
100µF
+
10V
TANT
* L1 IS A SINGLE CORE WITH TWO WINDINGS
COILTRONICS #CTX50-3A
† _{IF LOAD CAN GO TO ZERO, AN OPTIONAL}
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: 10MQ060N
D2
1N4148W
L1A*
50µH
R1
15.4k
R2
4.99k
D1
V_OUT1
5V
(SEE DN100
FOR MAX I_OUT)
+ ^C1
100µF
10V
TANT
L1B*
D3
C5 ₊
100µF
10V
TANT
1766 F14
V_OUT2
–5V^†
Figure 13. Buck Converter with Adjustable Soft-Start
Figure 14. Dual Output SEPIC Converter
DUAL OUTPUT SEPIC CONVERTER
The circuit in Figure 14 generates both positive and
negative 5V outputs with a single piece of magnetics. The
two inductors shown are actually just two windings on a
standard Coiltronics inductor. The topology for the 5V
output is a standard buck converter. The – 5V topology
would be a simple flyback winding coupled to the buck
converter if C4 were not present. C4 creates a SEPIC
(single-ended primary inductance converter) topology
which improves regulation and reduces ripple current in
L1. Without C4, the voltage swing on L1B compared to
L1A would vary due to relative loading and coupling
losses. C4 provides a low impedance path to maintain an
equal voltage swing in L1B, improving regulation. In a
flyback converter, during switch on time, all the converter’s
energy is stored in L1A only, since no current flows in L1B.
POSITIVE-TO-NEGATIVE CONVERTER
The circuit in Figure 15 is a positive-to-negative topology
using a grounded inductor. It differs from the standard
approach in the way the IC chip derives its feedback signal
because the LT1766 accepts only positive feedback sig-
nals. The ground pin must be tied to the regulated negative
output. A resistor divider to the FB pin then provides the
proper feedback voltage for the chip.
The following equation can be used to calculate maximum
load current for the positive-to-negative converter:
I_MAX
=
_IP
–
2(V_O⁽_U^VITN+^)(VVOINU)^T()f)(L) ^{(VOUT )(VIN}
(V_OUT + V_IN – 0.3)(V_OUT + V_F )
–
0.3)
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