LTM4637_15 Datasheet, PDF (22/30 Pages) Linear Technology – 20A DC/DC Module Step-Down Regulator

LTM4637
Applications Information
Table 6. Recommended Heat Sinks
HEAT SINK MANUFACTURER
PART NUMBER
AAVID Thermalloy
375424B00034G
Cool Innovations
4-050503P to 4-050508P
WEBSITE
www.aavidthermalloy.com
www.coolinnovations.com
Safety Considerations
The LTM4637 does not provide galvanic isolation from V_IN
to V_OUT. There is no internal fuse. If required, a slow blow
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic failure.
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internal top MOSFET fault. If the internal top MOSFET fails,
then turning it off will not resolve the overvoltage, thus
the internal bottom MOSFET will turn on indefinitely trying
to protect the load. Under this fault condition, the input
voltage will source very large currents to ground through
the failed internal top MOSFET and enabled internal bot-
tom MOSFET. This can cause excessive heat and board
damage depending on how much power the input voltage
can deliver to this system. A fuse or circuit breaker can be
used as a secondary fault protector in this situation. The
LTM4637 does support overvoltage protection, overcurrent
protection and overtemperature protection.
Layout Checklist/Example
The high integration of the LTM4637 makes the PCB
board layout very simple and easy. However, to optimize
its electrical and thermal performance, some layout
considerations are still necessary.
• Use large PCB copper areas for high current paths,
including V_IN, GND and V_OUT. It helps to minimize the
PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output
capacitors next to the V_IN, GND and V_OUT pins to
minimize high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put vias directly on the pad, unless they are
capped or plated over.
• Place test points on signal pins for testing.
• Use a separated SGND ground copper area for
components connected to signal pins. Connect the
SGND to GND underneath the unit.
• For parallel modules, tie the COMP and V_FB pins together.
Use an internal layer to closely connect these pins
together.
Figure 21 gives a good example of the recommended layout.
4637fc
22
For more information www.linear.com/LTM4637