LTC3856_15 Datasheet, PDF (22/40 Pages) Linear Technology – 2-Phase Synchronous Step-Down DC/DC Controller with Diffamp

LTC3856
Applications Information
The peak-to-peak MOSFET gate drive levels are set by the
voltage, V_CC, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BV_DSS specification for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less. Selection
criteria for the power MOSFETs include the on-resistance,
R_DS(ON), input capacitance, input voltage and maximum
output current. MOSFET input capacitance is a combination
of several components but can be taken from the typical
gate charge  c  urve included on most data sheets (Figure 9).
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage, then plotting the gate voltage versus time.
MILLER EFFECT
V_GS
a
b
Q_IN
C_MILLER = (Q_B – Q_A)/V_DS
V
+
V_GS
–
V_IN
+
– ^VDS
3856 F09
Figure 9. Gate Charge Characteristic
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given V_DS drain
voltage, but can be adjusted for different V_DS voltages by
multiplying the ratio of the application V_DS to the curve
specified V_DS values. A way to estimate the C_MILLER
term is to take the change in gate charge from points
a and b on a manufacturer’s data sheet and divide by
the stated V_DS voltage specified. C_MILLER is the most
important selection criteria for determining the transition
loss term in the top MOSFET but is not directly specified
on MOSFET data sheets. C_RSS and C_OS are specified
sometimes but definitions of these parameters are not
included. When the controller is operating in continuous
22
mode, the duty cycles for the top and bottom MOSFETs
are given by:
Main
Switch
Duty
Cycle
=
V_OUT
V_IN
Synchronous
Switch
Duty
Cycle
=


V_IN
– V_OUT
V_IN


The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
( ) ^P_MAIN
=
V_OUT
V_IN


I_MAX
N


2
1+ δ
R_DS(ON) +
( ) ( )( ) ^V_IN
2 ^ I_MAX ^
 ^2N 
R_DR
C_MILLER •



V_CC
1
– V_TH(IL)
+
1
V_TH(IL)



•
f
( ) ^P_SYNC
=
V_IN
– V_OUT
V_IN


I_MAX
N


2
1+ δ
R_DS(ON)
where N is the number of output stages, δ is the tem-
perature dependency of R_DS(ON), R_DR is the effective top
driver resistance (approximately 2Ω at V_GS = V_MILLER),
V_IN is the drain potential and the change in drain poten-
tial in the particular application. V_TH(IL) is the data sheet
specified typical gate threshold voltage specified in the
power MOSFET data sheet at the specified drain current.
C_MILLER is the calculated capacitance using the gate charge
curve from the MOSFET data sheet and the technique just
described.
Both MOSFETs have I²R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V_IN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for V_IN > 20V, the transition losses rapidly
increase to the point that the use of a higher R_DS(ON) device
with lower C_MILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low, or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
3856f