LTC2480 Datasheet, PDF (22/40 Pages) Linear Technology – 16-Bit ADC with Easy Drive

LTC2480
APPLICATIO S I FOR ATIO
External Serial Clock, 3-Wire I/O
This timing mode utilizes a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or transmission over an isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically 4ms after V_CC exceeds approximately 2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. The input data is then shifted in via the SDI
pin on the rising edge of SCK (including the first rising
edge) and the output data is shifted out of the SDO pin on
each falling edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 24th falling edge of SCK, SDO
goes HIGH (EOC = 1) indicating a new conversion has
begun. In applications where the processor generates 32
clock cycles, or to remain compatible with higher resolu-
tion converters, the LTC2480’s digital interface will ignore
extra clock edges seen during the next conversion period
after the 24th and outputs “1” for the extra clock cycles.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
2.7V TO 5.5V
1µF
2
V_CC
10
F_O
REFERENCE
VOLTAGE
0.1V TO V_CC
ANALOG
INPUT
LTC2480
3
V_REF
1
SDI
9
SCK
4 _IN+
5 _IN–
7
SDO
6
CS
8
GND
INT/EXT CLOCK
3-WIRE
SPI INTERFACE
CS
BIT 23 BIT 22
BIT 21
BIT 20
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
BIT 0
SDO
EOC
SIG
MSB
LSB
IM
SCK
(EXTERNAL)
SDI*
CONVERSION
DON’T CARE
22
EN
GS2
GS1
GS0
IM
FA
FB
SPD
DATA OUTPUT
Figure 7. External Serial Clock, CS = 0 Operation
DON’T CARE
CONVERSION
2480 F07
2480f