LTC2433-1 Datasheet, PDF (22/28 Pages) Linear Integrated Systems – Differential Input 16-Bit No Latency DS ADC

LTC2433-1
APPLICATIO S I FOR ATIO
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN⁺ and IN^– and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the con-
verter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large C_IN capacitor
values, it is advisable to carefully match the source imped-
ance seen by the IN⁺ and IN^– pins. When F_O = LOW
(internal oscillator and 50Hz/60Hz notch), every 180Ω
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 1LSB. When F_O is driven by an external oscillator
with a frequency f_EOSC, every 1Ω mismatch in source
impedance transforms a full-scale common mode input
signal into a differential mode input signal of 3.7 • 10^–8
• f_EOSCLSB. Figure 18 shows the typical offset error due to
input common mode voltage for various values of source
resistance imbalance between the IN⁺ and IN^– pins when
large C_IN values are used.
3
A
2
B
1
C
0D
E
V_CC
REF
= 5V
+ _{= 5V}
REF ^– = GND
IN⁺ = IN^– = V_INCM
–1
F
F_O = GND
–2
T_A = 25°C
G
R_SOURCEIN– = 500Ω
–3
C_IN = 10µF
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
V_INCM (V)
A: ∆R_IN = +400Ω
B: ∆R_IN = +200Ω
C: ∆R_IN = +100Ω
D: ∆R_IN = 0Ω
E: ∆R_IN = –100Ω
F: ∆R_IN = –200Ω
G: ∆R_IN = –400Ω
24331 F18
Figure 18. Offset Error vs Common Mode Voltage
(V_INCM = IN⁺ = IN^–) and Input Source Resistance
Imbalance (∆R_IN = R_SOURCEIN+ – R_SOURCEIN–) for
Large C_IN Values (C_IN ≥ 1µF)
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN⁺ and
IN^–, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 15k source resistance will create
a 0LSB typical and 1LSB maximum offset voltage.
Reference Current
In a similar fashion, the LTC2433-1 samples the differen-
tial reference pins REF⁺ and REF^– transfering small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (C_REF < 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C_REF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
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