LTC2240-12_15 Datasheet, PDF (22/30 Pages) Linear Technology – 12-Bit, 170Msps ADC

LTC2240-12
APPLICATIONS INFORMATION
In the CMOS output mode, OV_DD can be powered with
any voltage up to 2.625V. OGND can be powered with any
voltage from GND up to 1V and must be less than OV_DD.
The logic outputs will swing between OGND and OV_DD.
In the LVDS output mode, OV_DD should be connected to
a 2.5V supply and OGND should be connected to GND.
Output Enable
The outputs may be disabled with the output enable pin,
OE. In CMOS or LVDS output modes OE high disables all
data outputs including OF and CLKOUT. The data access
and bus relinquish times are too slow to allow the outputs
to be enabled and disabled during full speed operation.
The output Hi-Z state is intended for use during long
periods of inactivity.
The Hi-Z state is not a truly open circuit; the output pins
that make an LVDS output pair have a 20k resistance be-
tween them. Therefore in the CMOS output mode, adjacent
data bits will have 20k resistance in between them, even
in the Hi-Z state.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V_DD and OE to V_DD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors
have to
and OE
recharge and stabilize. Connecting SHDN to
to GND results in nap mode, which typically
V_DD
dis-
sipates 28mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap mode all digital outputs are disabled
and enter the Hi-Z state.
GROUNDING AND BYPASSING
The LTC2240-12 requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with
an internal ground plane is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
signal alongside an analog signal or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the V_DD, OV_DD, V_CM, REFHA, REFHB, REFLA and REFLB
pins. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capaci-
tors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recommended. The 2.2μF capacitor between REFHA
and REFLA can be somewhat further away. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2240-12 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
HEAT TRANSFER
Most of the heat generated by the LTC2240-12 is trans-
ferred from the die through the bottom-side exposed pad
and package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad should
be soldered to a large grounded pad on the PC board. It
is critical that all ground pins are connected to a ground
plane of sufficient area.
Clock Sources for Undersampling
Undersampling is especially demanding on the clock
source and the higher the input frequency, the greater the
sensitivity to clock jitter or phase noise. A clock source that
degrades SNR of a full-scale signal by 1dB at 70MHz will
degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a canned oscillator from vendors such as Saronix or Vec-
tron can be placed close to the ADC and simply connected
directly to the ADC. If there is any distance to the ADC,
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