LTC2180_15 Datasheet, PDF (22/36 Pages) Linear Technology – 16-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs

LTC2182/LTC2181/LTC2180
APPLICATIONS INFORMATION
LTC2182
V_DD
V_DD
DIFFERENTIAL
COMPARATOR
15k
ENC⁺
ENC^–
30k
218210 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
LTC2182
1.8V TO 3.3V
0V
ENC⁺
ENC^–
30k
CMOS LOGIC
BUFFER
218210 F11
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
0.1µF
T1
50Ω
0.1µF
50Ω
ENC⁺
LTC2182
100Ω
0.1µF ENC–
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
218210 F12
PECL OR
LVDS
CLOCK
0.1µF
ENC⁺
0.1µF
ENC^–
LTC2182
218210 F13
Figure 13. PECL or LVDS Encode Drive
22
mode, ENC^– should stay at least 200mV above ground to
avoid falsely triggering the single ended encode mode.
For good jitter performance ENC⁺ and ENC^– should have
fast rise and fall times.
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC^– is connected
to ground and ENC⁺ is driven with a square wave encode
input. ENC⁺ can be taken above V_DD (up to 3.6V) so 1.8V
to 3.3V CMOS logic levels can be used. The ENC⁺ threshold
is 0.9V. For good jitter performance ENC⁺ should have fast
rise and fall times.
If the encode signal is turned off or drops below approxi-
mately 500kHz, the A/D enters nap mode.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency, the duty cycle stabilizer circuit
requires one hundred clock cycles to lock onto the input
clock. The duty cycle stabilizer is enabled by mode control
register A2 (serial programming mode), or by CS (parallel
programming mode).
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle. The
duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2182/LTC2181/LTC2180 can operate in three digital
output modes: full rate CMOS, double data rate CMOS (to
halve the number of output lines), or double data rate LVDS
(to reduce digital noise in the system.) The output mode
is set by mode control register A3 (serial programming
mode), or by SCK (parallel programming mode). Note that
double data rate CMOS cannot be selected in the parallel
programming mode.
218210f