LTM4628 Datasheet, PDF (21/36 Pages) Linear Technology – Dual 8A or Single 16A DC/DC μModule Regulator

Applications Information
LTM4628
JUNCTION
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
AMBIENT
µMODULE DEVICE
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Figure 10. Graphical Representation of JESD 51-12 Thermal Coefficients
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
for θ_JCtop and θ_JCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4628, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
values supplied in this data sheet: (1) Initially, FEA software
is used to accurately build the mechanical geometry of
the LTM4628 and the specified PCB with all of the cor-
rect material coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
defined JEDEC environment consistent with JESD 51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4628 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulate conditions
with thermocouples within a controlled environment
chamber while operating the device at the same power
loss as that which was simulated. The outcome of this
process and due diligence yields a set of derating curves
provided in other sections of this data sheet. After these
laboratory tests have been performed the θ_JB and θ_BA are
summed together to correlate quite well with the LTM4628
model with no airflow or heat sinking in a properly de-
fined chamber. This θ_JB + θ_BA value is shown in the Pin
Configuration section and should accurately equal the θ_JA
value because approximately 100% of power loss flows
from the junction through the board into ambient with no
airflow or top mounted heat sink.
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