LTC3879_15 Datasheet, PDF (21/28 Pages) Linear Technology – Fast, Wide Operating Range No RSENSE Step-Down Controller

LTC3879
APPLICATIONS INFORMATION
inductor ripple current and load steps. The output voltage
ripple is given as:
( ) ΔV_OUT(RIPPLE) = ΔI_L(MAX) ESR
= 5.1• 4.5mΩ = 23mV
However, a 0A to 10A load step will cause an output
change of up to:
( ) ΔV_OUT(STEP) = ΔI_LOAD ESR
= 10A • 4.5mΩ = 45mV
Optional 2 × 47μF ceramic output capacitors are included
to minimize the effect of ESR and ESL in the output ripple
and to improve load step response.
PC Board Layout Checklist
The LTC3879 PC board layout can be designed with or
without a ground plane. A ground plane is generally pre-
ferred based on performance and noise concerns.
When using a ground plane, use a dedicated ground plane
layer. In addition, for high current it is recommended to
use a multilayer board to help with heat sinking power
components.
l The ground plane layer should have no traces and be
as close as possible to the routing layer connecting the
power MOSFET’s.
l Place LTC3879 Pins 9 to 16 facing the power compo-
nents. Keep components connected to Pin 1 close to
LTC3879 (noise sensitive components).
l Place C_IN, C_OUT, MOSFETs, D_B and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
l Use an immediate via to connect components to the
ground plane SGND and PGND of LTC3879. Use several
larger vias for power components.
l Use compact switch node (SW) plane to improve cool-
ing of the MOSFETs and to keep EMI down.
l Use planes for V_IN and V_OUT to maintain good voltage
filtering and to keep power losses low.
l Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
component. You can connect the copper areas to any
DC net. (V_IN, V_OUT, GND or to any other DC rail in your
system).
l Place decoupling capacitor C_C2 next to the I_TH and SGND
pins with short, direct trace connections.
When laying out a printed circuit board without a ground
plane, use the following checklist to ensure proper op-
eration of the controller. These items are illustrated in
Figure 11.
l Segregate the signal and power grounds. All small-signal
components should return to the SGND pin at one point.
SGND and PGND should be tied together underneath
the IC and then connect directly to the source of M2.
l Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
l Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
l Connect the input capacitor(s), C_IN, close to the
power MOSFETs. This capacitor carries the MOSFET AC
current.
l Connect the INTV_CC decoupling capacitor C_VCC closely
to the INTV_CC and PGND pins.
l Connect the top driver boost capacitor, C_B, closely to
the BOOST and SW pins.
l Connect the V_IN pin decoupling C_F closely to the V_IN
and PGND pins.
3879f
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