LTC3850-2 Datasheet, PDF (21/36 Pages) Linear Technology – Dual, 2-Phase Synchronous Step-Down Switching Controller

LTC3850-2
APPLICATIONS INFORMATION
both controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the dual
controller design. Also, the input protection fuse resistance,
battery resistance, and PC board trace resistance losses
are also reduced due to the reduced peak currents in a 2-
phase system. The overall benefit of a multiphase design
will only be fully realized when the source impedance of the
power supply/battery is included in the efficiency testing.
The sources of the top MOSFETs should be placed within
1cm of each other and share a common C_IN(s). Separating
the sources and C_IN may produce undesirable voltage and
current resonances at V_IN.
A small (0.1μF to 1μF) bypass capacitor between the chip
V_IN pin and ground, placed close to the LTC3850-2, is also
suggested. A 2.2Ω – 10Ω resistor placed between C_IN
(C1) and the V_IN pin provides further isolation between
the two channels.
The selection of C_OUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔV_OUT) is approximated by:
ΔV_OUT
≈ I_RIPPLE
⎛
⎝⎜ ^ESR
+
1
8fC_OUT
⎞
⎠⎟
where f is the operating frequency, C_OUT is the output
capacitance and I_RIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since I_RIPPLE increases with input voltage.
Setting Output Voltage
The LTC3850-2 output voltages are each set by an exter-
nal feedback resistive divider carefully placed across the
output, as shown in Figure 9. The regulated output voltage
is determined by:
V_OUT
=
0.8V
•
⎛
⎝⎜
1+
R_B
R_A
⎞
⎠⎟
V_OUT
1/2 LTC3850-2
V_FB
R_B
C_FF
R_A
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Figure 9. Setting Output Voltage
To improve the frequency response, a feed-forward ca-
pacitor, C_FF, may be used. Great care should be taken to
route the V_FB line away from noise sources, such as the
inductor or the SW line.
Fault Conditions: Current Limit and Current Foldback
The LTC3850-2 includes current foldback to help limit
load current when the output is shorted to ground. If the
output falls below 50% of its nominal output level, then
the maximum sense voltage is progressively lowered from
its maximum programmed value to one-third of the maxi-
mum value. Foldback current limiting is disabled during
the soft-start or tracking up. Under short-circuit condi-
tions with very low duty cycles, the LTC3850-2 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuit ripple current is determined by the minimum
on-time t_ON(MIN) of the LTC3850-2 (≈ 90ns), the input
voltage and inductor value:
ΔI_L(SC)
=
t_ON(MIN)
•
V_IN
L
The resulting short-circuit current is:
I_SC
=
1/3
V_{SENSE(MAX )}
R_SENSE
–
1
2
ΔI_L(SC)
Phase-Locked Loop and Frequency Synchronization
The LTC3850-2 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (V_CO) and a phase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The turn-on
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