LTC2260-12_15 Datasheet, PDF (21/34 Pages) Linear Technology – 12-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs

LTC2261-12
LTC2260-12/LTC2259-12
Applications Information
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10) and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinu-
soidal, PECL or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken
above V_DD (up to 3.6V), and the common mode range
is from 1.1V to 1.6V. In the differential encode mode,
ENC^– should stay at least 200mV above ground to avoid
falsely triggering the single-ended encode mode. For good
jitter performance ENC⁺ and ENC^– should have fast rise
and fall times.
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC^– is connected
to ground and ENC⁺ is driven with a square wave encode
input. ENC⁺ can be taken above V_DD (up to 3.6V) so 1.8V
to 3.3V CMOS logic levels can be used. The ENC⁺ threshold
is 0.9V. For good jitter performance ENC⁺ should have fast
rise and fall times.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50%(±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
by mode control register A2 (serial programming mode),
or by CS (parallel programming mode).
LTC2261-12
V_DD
V_DD
15k
ENC⁺
ENC^–
30k
DIFFERENTIAL
COMPARATOR
226112 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
LTC2261-12
1.8V TO 3.3V
0V
ENC⁺
ENC^–
30k
CMOS LOGIC
BUFFER
226112 F11
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
25Ω
D1
0.1µF
T1
1:4
T1: COILCRAFT WBC4 - 1WL
D1: AVAGO HSMS - 2822
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
100Ω
100Ω
ENC⁺
LTC2261-12
ENC^–
0.1µF
226112 F12
Figure 12. Sinusoidal Encode Drive
PECL OR
LVDS
CLOCK
0.1µF
ENC⁺
0.1µF
ENC^–
LTC2261-12
226112 F13
Figure 13. PECL or LVDS Encode Drive
For more information www.linear.com/LTC2261-12
226112fc
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