LTC2240-10_15 Datasheet, PDF (21/28 Pages) Linear Technology – 10-Bit, 170Msps ADC

LTC2240-10
APPLICATIONS INFORMATION
LTC2240-10
V_DD
DATA
FROM
LATCH
PREDRIVER
LOGIC
OE
OV_{DD 0.5V}
LTC2240-10
V_DD
TO 2.625V
0.1μF
OV_DD
2.5V
0.1μF
OV_DD
43Ω
TYPICAL
DATA
OUTPUT
OGND
D
10k 10k
1.25V
D
D
OUT⁺
100Ω
OUT^–
D
LVDS
RECEIVER
224010 F13a
3.5mA
OGND
Figure 13a. Digital Output Buffer in CMOS Mode
224010 F13b
Figure 13b. Digital Output in LVDS Mode
Data Format
The LTC2240-10 parallel digital output can be selected
for offset binary or 2’s complement format. The format
is selected with the MODE pin. Connecting MODE to GND
or 1/3V_DD selects offset binary output format. Connecting
MODE to 2/3V_DD or V_DD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3V_DD or 2/3V_DD logic values. Table 3 shows the logic
states for the MODE pin.
Table 3. MODE Pin Function
MODE PIN
GND
1/3V_DD
2/3V_DD
V_DD
OUTPUT FORMAT
Offset Binary
Offset Binary
2’s Complement
2’s Complement
CLOCK DUTY
CYCLE STABILIZER
Off
On
On
Off
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overflow or underflow on the
A data bus, while a logic high on the OFB pin indicates an
overflow or underflow on the B data bus. In LVDS mode,
a differential logic high on the OF⁺/OF^– pins indicates an
overflow or underflow.
Output Clock
The ADC has a delayed version of the ENC⁺ input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal encode. In
all CMOS modes, A bus data will be updated just after
CLKOUTA rises and can be latched on the falling edge of
CLKOUTA. In demux CMOS mode with interleaved update,
B bus data will be updated just after CLKOUTB rises and
can be latched on the falling edge of CLKOUTB. In demux
CMOS mode with simultaneous update, B bus data will be
updated just after CLKOUTB falls and can be latched on
the rising edge of CLKOUTB. In LVDS mode, data will be
updated just after CLKOUT⁺/CLKOUT^– rises and can be
latched on the falling edge of CLKOUT⁺/CLKOUT^–.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV_DD, should be tied
to the same power supply as for the logic being driven.
For example if the converter is driving a DSP powered
by a 1.8V supply then OV_DD should be tied to that same
1.8V supply.
224010fb
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