LTC1871-7 Datasheet, PDF (21/32 Pages) Linear Technology – High Input Voltage,Current Mode Boost, Flyback and SEPIC Controller

LTC1871-7
APPLICATIONS INFORMATION
The component chosen is a 6.8μH inductor made by
Cooper (part number DR127-6R8) which has a satura-
tion current of greater than 13.3A.
5. Because the duty cycle is 81%, the maximum SENSE
pin threshold voltage is reduced from its low duty cycle
typical value of 150mV to approximately 115mV. In ad-
dition, we need to apply a worst-case derating factor
to this SENSE threshold to account for manufacturing
tolerances within the IC. Finally, the nominal current
limit value should exceed the maximum load current
by some safety margin (in this case 50%). Therefore,
the value of the sense resistor is:
R_SENSE
=
0.8
•
V_SENSE(MAX)
•


1+
1– D_MAX
0.4 
2 
•
1.5
•
I_O(MAX)
=
0.8
•
0.115
•
1– 0.81
1.2 • 1.5 • 1.5
=
6.5m

A 1W, 5mΩ resistor is used in this design.
6. The MOSFET chosen is a Vishay/Siliconix Si7370DP,
which has a BV_DSS of greater than 60V and an R_DS(ON)
of less than 13mΩ at a V_GS of 6V.
7. The diode for this design must handle a maximum DC
output current of 1.5A and be rated for a minimum
reverse voltage of V_OUT, or 42V. A 3A, 60V diode from
Diodes Inc. (B360B) is chosen.
8. The output capacitor usually consists of a high valued
bulk C connected in parallel with a lower valued, low
ESR ceramic. Based on a maximum output ripple voltage
of 1%, or 50mV, the bulk C needs to be greater than:
C_OUT


I_OUT(MAX)
0.01• V_OUT •
f
=
0.01•
1.5
42 •
250k
=
14μF
The RMS ripple current rating for this capacitor needs
to exceed:
I_RMS(COUT)
I_O(MAX) •
V_O – V_IN(MIN)
V_IN(MIN)
=
1.5 •
42 –
8
8
=
3.09A
To satisfy the low ESR, high frequency decoupling
requirements, two 10μF, 50V, X5R ceramic capacitors
are used (TDK part number C5750X5R1H106M). In
parallel with these, two 68μF, 100V electrolytic ca-
pacitors are used (Sanyo part number 100CV68FS).
Check the output ripple with a single oscilloscope
probe connected directly across the output capacitor
terminals, where the HF switching currents flow.
9. The choice of an input capacitor for a boost converter
depends on the impedance of the source supply and
the amount of input ripple the converter will safely
tolerate. For this particular design and lab setup a
560μF, 50V Sanyo electrolytic (50MV560AXL), in
parallel with two 10μF, 100V TDK ceramic capacitors
(C5750X5R1H106M) is required (the input and return
lead lengths are kept to a few inches, but the peak input
current is close to 10A!). As with the output node,
check the input ripple with a single oscilloscope probe
connected across the input capacitor terminals.
V_OUT
1V/DIV
I_L
2A/DIV
MOSFET
DRAIN
VOLTAGE
20V/DIV
V_IN = 8V
I_OUT = 0.5A
V_OUT = 42V
D = 81%
1μs/DIV
18717 F15
Figure 15. Switching Waveforms for the Converter
in Figure 9 at Minimum V_IN (8V)
18717fc
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