LT3652 Datasheet, PDF (21/26 Pages) Linear Technology – Power Tracking 2A Battery Charger for Solar Power

LT3652
APPLICATIONS INFORMATION
In some cases, the thermal foldback protection feature
can reduce charger currents below the C/10 threshold. In
applications that use C/10 termination (TIMER=0V), the
LT3652 will suspend charging and enter standby mode
until the excessive temperature condition is relieved.
Layout Considerations
The LT3652 switch node has rise and fall times that are
typically less than 10nS to maximize conversion efficiency.
The switch node (Pin SW) trace should be kept as short
as possible to minimize high frequency noise. The input
capacitor (C_IN) should be placed close to the IC to minimize
this switching noise. Short, wide traces on these nodes
also help to avoid voltage stress from inductive ringing.
The BOOST decoupling capacitor should also be in close
proximity to the IC to minimize inductive ringing. The
SENSE and BAT traces should be routed together, and
these and the V_FB trace should be kept as short as pos-
sible. Shielding these signals from switching noise with
a ground plane is recommended.
High current paths and transients should be kept iso-
lated from battery ground, to assure an accurate output
voltage reference. Effective grounding can be achieved
by considering switched current in the ground plane,
and careful component placement and orientation can
effectively steer these high currents such that the battery
reference does not get corrupted. Figure 11 illustrates an
effective grounding scheme using component placement
to control ground currents. When the switch is enabled
(loop #1), current flows from the input bypass capacitor
(C_IN) through the switch and inductor to the battery posi-
tive terminal. When the switch is disabled (loop #2), the
current to the battery positive terminal is provided from
ground through the freewheeling Schottky diode (D_F). In
both cases, these switch currents return to ground via the
output bypass capacitor (C_BAT).
The LT3652 packaging has been designed to efficiently
remove heat from the IC via the Exposed Pad on the
backside of the package, which is soldered to a copper
footprint on the PCB. This footprint should be made as
large as possible to reduce the thermal resistance of the
IC case to ambient air.
C_IN
C_BAT
1
2
D_F
LT3652
V_IN
SW
SENSE
BAT
V_FB
R_SENSE
V_BAT
+
3652 F11
Figure 11. Component Orientation Isolates High Current Paths
from Sensitive Nodes
3652fb
21