LT1956EFE-5 Datasheet, PDF (21/28 Pages) Linear Technology – High Voltage, 1.5A, 500kHz Step-Down

LT1956/LT1956-5
APPLICATIO S I FOR ATIO
Input Voltage vs Operating Frequency Considerations
The absolute maximum input supply voltage for the LT1956
is specified at 60V. This is based on internal semiconduc-
tor junction breakdown effects. The practical maximum
input supply voltage for the LT1956 may be less than 60V
due to internal power dissipation or switch minimum on
time considerations.
For the extreme case of an output short-circuit fault to
ground, see the section Short-Circuit Considerations.
A detailed theoretical basis for estimating internal power
dissipation is given in the Thermal Calculations section.
This will allow a first pass check of whether an application’s
maximum input voltage requirement is suitable for the
LT1956. Be aware that these calculations are for DC input
voltages and that input voltage transients as high as 60V
are possible if the resulting increase in internal power
dissipation is of insufficient time duration to raise die
temperature significantly. For the FE package, this means
high voltage transients on the order of hundreds of milli-
seconds are possible. If LT1956 (FE package) thermal
calculations show power dissipation is not suitable for the
given application, the LT1766 (FE package) is a recom-
mended alternative since it is identical to the LT1956 but
runs cooler at 200kHz.
Switch minimum on time is the other factor that may limit
the maximum operational input voltage for the LT1956 if
pulse-skipping behavior is not allowed. For the LT1956,
pulse-skipping may occur for V_IN/(V_OUT + V_F) ratios > 4.
(V_F = Schottky diode D1 forward voltage drop, Figure 5.)
If the LT1766 is used, the ratio increases to 10. Pulse-
skipping is the regulator’s way of missing switch pulses to
maintain output voltage regulation. Although an increase
in output ripple voltage can occur during pulse-skipping,
a ceramic output capacitor can be used to keep ripple
voltage to a minimum (see output ripple voltage compari-
son for tantalum vs ceramic output capacitors, Figure 3).
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits, read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/
or catch diode, and connecting the V_C compensation to a
ground track carrying significant switch current. In addi-
tion, the theoretical analysis considers only first order
non-ideal component behavior. For these reasons, it is
important that a final stability check is made with produc-
tion layout and components.
The LT1956 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 10.
The LT1956 can be considered as two g_m blocks, the error
amplifier and the power stage.
Figure 11 shows the overall loop response. At the V_C pin,
the frequency compensation components used are:
R_C = 2.2k, C_C = 0.022µF and C_F = 220pF. The output
capacitor used is a 100µF, 10V tantalum capacitor with
typical ESR of 100mΩ.
The ESR of the tantalum output capacitor provides a useful
zero in the loop frequency response for maintaining stabil-
ity. This ESR, however, contributes significantly to the
ripple voltage at the output (see Output Ripple Voltage in
the Applications Information section). It is possible to
reduce capacitor size and output ripple voltage by replac-
ing the tantalum output capacitor with a ceramic output
capacitor because of its very low ESR. The zero provided
by the tantalum output capacitor must now be reinserted
back into the loop. Alternatively, there may be cases
where, even with the tantalum output capacitor, an addi-
tional zero is required in the loop to increase phase margin
for improved transient response.
A zero can be added into the loop by placing a resistor (R_C)
at the V_C pin in series with the compensation capacitor, C_C,
or by placing a capacitor (C_FB) between the output and the
FB pin.
When using R_C, the maximum value has two limitations.
First, the combination of output capacitor ESR and R_C may
stop the loop rolling off altogether. Second, if the loop gain
is not rolled off sufficiently at the switching frequency,
output ripple will perturb the V_C pin enough to cause
unstable duty cycle switching similar to subharmonic
1956f
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